aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/AVR
AgeCommit message (Expand)AuthorFilesLines
2025-10-24[AVR] Fix occasional corruption in stack passed paramsCarl Peto2-10/+42
2025-08-12[Test] Add and update tests for `lrint`/`llrint` (NFC) (#152662)Trevor Gross2-4/+40
2025-08-10[AVR] Change `half` to use `softPromoteHalfType` (#152783)Trevor Gross2-138/+69
2025-08-10[AVR][NFC] Add a test for fp16 support (#152708)Trevor Gross1-0/+593
2025-08-09[AVR] Fix Avr indvar detection and strength reduction (missed optimization) (...Tom Vijlbrief5-10/+139
2025-08-07[AVR] Fix codegen after getConstant assertions got enabled (#152269)Ayke1-0/+15
2025-08-04RuntimeLibcalls: Really move default libcall handling to tablegen (#148780)Matt Arsenault1-827/+356
2025-07-25AVR: Add llvm.sincos intrinsic test (#148601)Matt Arsenault1-0/+883
2025-07-20[AVR] Force to emit relocation slots for relative branch instructions (#145291)Tom Vijlbrief3-27/+14
2025-07-14[AVR] Simplify SPWRITE on XMEGA (#147210)Tom Vijlbrief1-0/+47
2025-07-09DAG: Fall back to separate sin and cos when softening sincos (#147468)Matt Arsenault1-0/+9
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David1-17/+17
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David1-17/+17
2025-06-22[AVR] Don't apply post-indexing on mismatched pointers (#145224)Patryk Wychowaniec1-0/+36
2025-06-11Introduce MCAsmInfo::UsesSetToEquateSymbol and prefer = to .setFangrui Song1-14/+14
2025-05-22[LangRef] Comment on validity of volatile ops on null (#139803)Luigi Sartor Piucco1-0/+15
2025-04-23[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)Ben Shi1-0/+6
2025-04-14[RegAlloc] Sort CopyHint by IsCSR (#131046)Michael Maitland4-24/+20
2025-03-26[AVR] Fix a bug in selection of ANY_EXTEND (#132398)Ben Shi3-20/+96
2025-03-26[AVR][NFC] Simplify branch relaxation tests (#131871)Patryk Wychowaniec2-4100/+2
2025-02-05PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)Matt Arsenault1-36/+36
2025-01-20[AVR] Force relocations for non-encodable jumps (#121498)Patryk Wychowaniec2-4/+18
2024-12-27[AVR] Wrap out-of-bounds relative jumps (#118015)Patryk Wychowaniec3-4162/+4162
2024-12-22[CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamerFangrui Song1-1/+0
2024-12-15[AVR,test] Change llc -march= to -mtriple=Fangrui Song92-114/+114
2024-12-05[AVR] Simplify eocoding of load/store instructions (#118279)Ben Shi1-0/+26
2024-10-18[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::has...Alex Rønne Petersen1-0/+20
2024-08-30[AVR] Fix parsing & emitting relative jumps (#106722)Patryk Wychowaniec1-0/+25
2024-08-29[AVR] Fix 16-bit LDDs with immediate overflows (#104923)Patryk Wychowaniec2-0/+281
2024-05-29[MachineLICM] Hoist copies of constant physical register (#93285)Pengcheng Wang1-3/+3
2024-04-15[SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset (#88493)fengfeng1-0/+18
2024-03-15[AVR] Remove earlyclobber from LDDRdPtrQ (#85277)Patryk Wychowaniec1-0/+163
2024-02-05[AVR] Convert tests to opaque pointers (NFC)Nikita Popov53-583/+573
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-9/+9
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-9/+9
2023-10-02[AVR] Fix a crash in AVRInstrInfo::insertIndirectBranch (#67324)Ben Shi2-4/+47
2023-09-15[RA] Split a virtual register in cold blocks if it is not assigned preferred ...Guozhi Wei1-3/+2
2023-09-11[test] Change llc -march= to -mtriple=Fangrui Song4-8/+8
2023-07-24[CodeGen] Add machine verification to some testsJay Foad1-1/+1
2023-07-19[AVR] Expand shifts of all types except int8 and int16Patryk Wychowaniec2-37/+134
2023-07-19[AVR] Enable verifyInstructionPredicates for AVRJianjian GUAN1-1/+1
2023-06-11[AVR] Optimize 8-bit rotation when rotation bits == 3Ben Shi1-15/+7
2023-06-11[AVR] Optimize 8-bit rotation when rotation bits >= 4Ben Shi1-55/+7
2023-06-11[AVR] Fix incorrect expansion of pseudo instruction ROLBRdBen Shi3-41/+82
2023-06-11[AVR] Enable sub register livenessBen Shi2-11/+5
2023-06-11[AVR][NFC] Improve CodeGen testsBen Shi1-15/+26
2023-06-06[AVR][NFC][test] Supplement more tests of 8-bit rotationBen Shi1-8/+104
2023-06-04[AVR][NFC][test] Suppement a test of the pseudo instruction RORBRdBen Shi1-0/+25
2023-06-04[AVR] Fix incorrect operands of pseudo instruction 'ROLBRd'Patryk Wychowaniec2-6/+231
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta1-1/+1