| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2026-02-11 | [X86] Move getTargetVShift helpers earlier in the source file. NFC. (#180972) | Simon Pilgrim | 1 | -168/+170 |
| 2026-02-10 | [NewPM] Port x86-insert-x87-wait (#180128) | Kyungtak Woo | 6 | -14/+31 |
| 2026-02-10 | [NewPM] Port x86-winehstate (#180687) | Anshul Nigham | 5 | -49/+95 |
| 2026-02-11 | [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (#180472) | woruyu | 1 | -3/+11 |
| 2026-02-10 | [X86] SimplifyDemandedVectorEltsForTargetNode - add handling for vpmaddwd/vpm... | Simon Pilgrim | 1 | -0/+3 |
| 2026-02-10 | [X86] Fixed flags issue of onlyZeroFlagUsed (#180405) | JaydeepChauhan14 | 1 | -1/+5 |
| 2026-02-09 | [NewPM] Port x86-global-base-reg (#180119) | Kyungtak Woo | 7 | -109/+157 |
| 2026-02-09 | [X86] Fold expand(splat,passthrough,mask) -> select(splat,passthrough,mask) (... | Simon Pilgrim | 1 | -0/+4 |
| 2026-02-09 | [CostModel][X86] getShuffleCost - SK_Transpose v4f64/v4i64 matches UNPCK - do... | Simon Pilgrim | 1 | -1/+8 |
| 2026-02-09 | [X86] Allow handling of i128/256/512 SELECT on the FPU (#180197) | Simon Pilgrim | 1 | -0/+36 |
| 2026-02-09 | [X86] Optimized ADC + ADD to ADC (#176713) | JaydeepChauhan14 | 1 | -2/+6 |
| 2026-02-09 | [SelectionDAGBuilder] Remove NoNaNsFPMath uses (#169904) | paperchalice | 1 | -2/+5 |
| 2026-02-08 | [X86] optimize 512-bit masked truncated saturating stores (#179130) | Folkert de Vries | 1 | -1/+2 |
| 2026-02-07 | [X86] AMD Zen 6 Initial enablement (#179150) | Ganesh | 2 | -0/+12 |
| 2026-02-06 | Add llvm.cond.loop intrinsic. | Peter Collingbourne | 6 | -23/+55 |
| 2026-02-06 | [NewPM] Uninitialize x86-cleanup-local-dynamic-tls in llvm/lib/Target/X86/X86... | Kyungtak Woo | 1 | -1/+0 |
| 2026-02-06 | [NewPM] Port x86-indirect-branch-tracking (#179874) | Kyungtak Woo | 5 | -37/+51 |
| 2026-02-06 | [X86] combineSetCC - attempt to match more complex icmp_eq/ne patterns before... | Simon Pilgrim | 1 | -6/+4 |
| 2026-02-06 | [NewPM] Port x86-cleanup-local-dynamic-tls (#179864) | Kyungtak Woo | 7 | -118/+178 |
| 2026-02-05 | [X86] mayFoldIntoVector - ensure we check for custom lowering to logic/add/su... | Simon Pilgrim | 1 | -17/+25 |
| 2026-02-05 | [X86] Fixed truncated masked stores (#179853) | Phoebe Wang | 1 | -2/+10 |
| 2026-02-05 | [X86] lower1BitShuffle - recognise a blend shuffle that can lower to AND/MASK... | Simon Pilgrim | 1 | -0/+10 |
| 2026-02-04 | [NewPM] Port x86-lvi-load (#179371) | Anshul Nigham | 5 | -39/+86 |
| 2026-02-04 | [CodeGen] Remove unused first operand of SUBREG_TO_REG (#179690) | Jay Foad | 13 | -129/+100 |
| 2026-02-04 | [X86] Lower i512 ADD/SUB using Kogge-Stone on AVX512 (#174761) | Islam Imad | 1 | -2/+73 |
| 2026-02-04 | [X86] Fold EXPAND(X,Y,M) -> SELECT(M,X,Y) when M is a lowest bit mask (#179630) | Simon Pilgrim | 1 | -0/+9 |
| 2026-02-04 | [X86] computeKnownBitsForTargetNode - extend X86ISD::BZHI handling. Fixes 177... | Shamshura Egor | 1 | -1/+21 |
| 2026-02-04 | [X86] Fold vgf2p8affineqb XOR with splat constant into immediate (#179103) | bala-bhargav | 1 | -0/+28 |
| 2026-02-04 | [X86] Lower CTTZ/CTLZ vXi8 vectors using GF2P8AFFINEQB (#118012) | Simon Pilgrim | 1 | -28/+32 |
| 2026-02-04 | [NFC][LLVM] Make `constrainSelectedInstRegOperands` return `void` (#179501) | Juan Manuel Martinez Caamaño | 1 | -9/+14 |
| 2026-02-03 | [X86] mayFoldIntoVector - recognise larger than legal logic ops may fold to v... | Simon Pilgrim | 1 | -4/+6 |
| 2026-02-03 | [X86] Restrict offset folding into address mode in 16-bit mode (#179399) | Fangrui Song | 1 | -0/+5 |
| 2026-02-02 | [NewPM] Fix callsite for x86-lvi-ret (#179383) | Anshul Nigham | 1 | -3/+3 |
| 2026-02-02 | [CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (N... | Nicolai Hähnle | 2 | -24/+32 |
| 2026-02-02 | [NewPM] Port x86-wineh-unwindv2 (#179172) | Anshul Nigham | 5 | -36/+46 |
| 2026-02-02 | [X86][GISEL] Enable PostLegalize Combiner (#174696) | Mahesh-Attarde | 5 | -1/+202 |
| 2026-02-02 | [X86][APX] Disable PP2/PPX generation on Windows (#178122) | Phoebe Wang | 1 | -0/+3 |
| 2026-02-02 | [X86] checkSignTestSetCCCombine - handle SIGN_EXTEND_INREG/SHL patterns insid... | Abhiram Jampani | 1 | -4/+8 |
| 2026-02-01 | [NewPM] Port MachineDominanceFrontierAnalysis (#177709) | Anshul Nigham | 1 | -3/+3 |
| 2026-02-01 | [X86] getScalarMaskingNode - FIXUPIMM scalar ops take upper elements from sec... | Simon Pilgrim | 1 | -4/+6 |
| 2026-01-30 | [X86] Truncate unused bit for blendw mask (#178883) | Mahesh-Attarde | 1 | -1/+2 |
| 2026-01-29 | [X86] canonicalizeLaneShuffleWithRepeatedOps - avoid folding vperm2x128(vpshu... | Simon Pilgrim | 1 | -5/+12 |
| 2026-01-29 | [X86] Canonicalise insertps(insertps(v,s,c0),s,c1) patterns to blend(v,splat(... | Simon Pilgrim | 1 | -0/+17 |
| 2026-01-28 | [X86] LowerBUILD_VECTORvXbf16 - pull out repeated MVT::f16/bf16 selection. NF... | Simon Pilgrim | 1 | -4/+3 |
| 2026-01-28 | [X86] vectorizeExtractedCast - don't assume vector source type is simple (#17... | Simon Pilgrim | 1 | -2/+3 |
| 2026-01-28 | [CostModel][X86] reduce_add(vXi1) will lower as a scalar ctpop (#178400) | Simon Pilgrim | 1 | -0/+11 |
| 2026-01-28 | [X86] X86FixupInstTunings - attempt to convert VPERMQri to VINSERTI128rri (#1... | Julian Pokrovsky | 1 | -1/+41 |
| 2026-01-27 | [TTI] Add VectorInstrContext for context-aware insert/extract costs. (#175982) | Florian Hahn | 2 | -18/+25 |
| 2026-01-27 | [perf] Replace copy-assign by move-assign in llvm/lib/Target/* (#178179) | serge-sans-paille | 1 | -1/+1 |
| 2026-01-26 | [X86] combineX86FPLogicOp - attempt to fold FAND/FOR/FXOR scalar nodes if the... | Simon Pilgrim | 1 | -5/+17 |
