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path: root/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
AgeCommit message (Expand)AuthorFilesLines
2025-09-12[RISCV] Enabled debug entry support by default (#157703)Georgiy Samoylov1-0/+3
2025-09-12[RISCV] Move MachineCombiner to addILPOpts() (#158071)Pengcheng Wang1-3/+8
2025-09-11[llvm] Move data layout string computation to TargetParser (#157612)Reid Kleckner1-36/+4
2025-09-04Recommit "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#1...Craig Topper1-1/+2
2025-09-04Revert "[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156...Craig Topper1-2/+1
2025-09-04[RISCV] Don't run loop-idiom-vectorize pass in the O0 pipeline. (#156798)Craig Topper1-1/+2
2025-08-22[RISCV] Add initial assembler/MC layer support for big-endian (#146534)Djordje Todorovic1-11/+29
2025-08-17[llvm] Remove unused includes (NFC) (#154051)Kazu Hirata1-1/+0
2025-08-06[RISCV] add load/store misched/PostRA subtarget features (#149409)Daniel Henrique Barboza1-15/+10
2025-08-05[RISCV][EVL] Drop EVLIndVarSimplifyPass from the pipeline (#151483)Shih-Po Hung1-6/+0
2025-07-25[RISCV] Remove -riscv-enable-vl-optimizer flag (#149349)Luke Lau1-7/+1
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+2
2025-06-17[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (#139993)Jesse Huang1-1/+4
2025-06-03[RISCV][NFC] Simplify the creation of Scheduler (#142553)Pengcheng Wang1-7/+4
2025-06-03[MISched] Add templates for creating custom schedulers (#141935)Pengcheng Wang1-3/+3
2025-05-28[RISCV] Make RISCVIndirectBranchTracking visible in debug output (#141623)Jesse Huang1-0/+1
2025-05-14[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131...Min-Yih Hsu1-0/+7
2025-05-06Register assembly printer passes (#138348)Matthias Braun1-0/+1
2025-04-26[TTI] Simplify implementation (NFCI) (#136674)Sergei Barannikov1-1/+1
2025-04-03[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)Rahul Joshi1-0/+2
2025-03-27[RISCV] Add late optimization pass for riscv (#133256)Mikhail R. Gadelha1-0/+3
2025-03-07[RISCV] Generate MIPS load/store pair instructions (#124717)Djordje Todorovic1-0/+3
2025-02-20[RISCV] Move VMV0 elimination past machine SSA opts (#126850)Luke Lau1-6/+2
2025-02-19Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into loa...Craig Topper1-0/+2
2025-02-19Revert "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/...Craig Topper1-2/+0
2025-02-19[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store ad...Craig Topper1-0/+2
2025-02-12[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 ...Luke Lau1-0/+7
2025-02-07[RISCV] Fix typos discovered by codespell (NFC) (#126191)Sudharsan Veeravalli1-1/+1
2025-02-05[CodeGen] Move MISched target hooks into TargetMachine (#125700)Christudasan Devadasan1-33/+33
2025-01-28[RISCV] Add MIPS extensions (#121394)Djordje Todorovic1-0/+1
2024-12-19[RISCV] Add software pipeliner support (#117546)Pengcheng Wang1-0/+8
2024-12-17[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)Michael Maitland1-1/+1
2024-12-11[RISCV] Enable merging of external globals by default (#117880)Alex Bradbury1-9/+1
2024-12-10[RISCV] Add stack clash protection (#117612)Raphael Moreira Zinsly1-2/+2
2024-11-29[RISCV] Set a barrier between mask producer and user of V0 (#114012)Pengcheng Wang1-0/+11
2024-11-15[RISCV] Enable global merging by default (#115495)Alex Bradbury1-1/+7
2024-11-14Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)Matin Raayai1-3/+3
2024-11-11[RISCV] Remove unused includes (NFC) (#115814)Kazu Hirata1-2/+0
2024-11-09[RISCV] When using global merging, don't enable merging of external globals b...Alex Bradbury1-1/+9
2024-11-06[RISCV] Add load/store clustering in post machine schedule (#111504)BoyaoWang4301-0/+18
2024-11-06[RISCV][CFI] add function epilogue cfi information (#110810)dlav-sc1-0/+2
2024-10-28[RISCV] Remove support for pre-RA vsetvli insertion (#110796)Luke Lau1-18/+2
2024-10-14[RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)Luke Lau1-0/+1
2024-10-11[RISCV] Enable store clustering by default (#73796)Alex Bradbury1-4/+6
2024-10-11[RISCV] Introduce VLOptimizer pass (#108640)Michael Maitland1-1/+9
2024-10-01[RISCV][GISel] Add RISCVPassConfig::getCSEConfig() to match other targets. (#...Craig Topper1-0/+7
2024-10-01[RISCV] Enable load clustering by default (#73789)Alex Bradbury1-1/+1
2024-09-20Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"Michael Maitland1-2/+0
2024-09-19[RISCV] Add additional fence for amocas when required by recent ABI change (#...Alex Bradbury1-0/+1
2024-09-17[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)Michael Maitland1-0/+2
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