aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/RISCV/AsmParser
AgeCommit message (Expand)AuthorFilesLines
2026-02-10[RISCV] Generate 8alt/16alt version error message for zvfofp8min (#180450)Jim Lin1-0/+1
2026-02-05[RISCV] Call updateCZceFeatureImplications from RISCVAsmParser::setFeatureBit...Craig Topper1-2/+6
2026-02-02[RISCV] Fix register names for CM_MVSA01/QC_CM_MVSA01 check in RISCVAsmParser...Craig Topper1-3/+3
2026-01-30[RISCV] Rename ConstraintMask->RVVConstraintMask. NFC (#178963)Craig Topper1-1/+1
2026-01-26[RISC-V][Mach-O] Add assembler support for Mach-O relocations. (#177446)Francesco Petrogalli1-11/+11
2026-01-13[RISCV] AI Foundry ET extensions for RISC-V (#174571)Abel Bernabeu1-0/+9
2025-11-29[RISCV] Intrinsic Support for XCVelw (#129168)Qihan Cai1-0/+3
2025-11-17[RISCV] Remove Match_InvalidXSfmmVType. NFC (#168465)Craig Topper1-4/+0
2025-11-17[RISCV] Remove unused function declaration. NFC (#168459)Craig Topper1-1/+0
2025-11-11[RISCV] Remove implicit conversions of MCRegister to unsigned. NFC (#167588)Craig Topper1-27/+23
2025-10-21[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supp...Min-Yih Hsu1-1/+2
2025-10-15[ADT] Migrate StringSwitch Cases with 6+ arguments to new overload. NFC. (#16...Jakub Kuderski1-3/+3
2025-10-13[RISCV] Add XSfmm pseudo instruction and vset* insertion support (#143068)Brandon Wu1-0/+4
2025-10-12[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) (#163086)Kazu Hirata1-1/+1
2025-09-23[RISCV][NFC] Rename simm12 to simm12_lo (#160380)Sam Elliott1-1/+5
2025-09-21[RISCV][NFC] Parsed Immediates are Expressions (#159888)Sam Elliott1-110/+113
2025-09-12[RISCV][MC] Add MC support of Zibi experimental extension (#127463)Boyao Wang1-0/+9
2025-08-28[RISCV] Implement MC support for Zvfbfa extension (#151106)Jim Lin1-6/+21
2025-08-22[RISCV] Add initial assembler/MC layer support for big-endian (#146534)Djordje Todorovic1-0/+2
2025-08-17[RISCV] Accept [-128,255] instead of [0, 255] for pli.b (#153913)Craig Topper1-0/+12
2025-07-25[RISCV] Handle 'c.addi x0, $imm' alias for c.nop using PseudoC_ADDI_NOP. (#15...Craig Topper1-2/+7
2025-07-14[RISCV] Fix QC.E.LI -> C.LI with Bare Symbol Compression (#146763)Sam Elliott1-0/+4
2025-07-14[RISCV] Render P-ext simm10_unsigned as a simm10 after parsing. (#148749)Craig Topper1-0/+8
2025-07-04MCParser: Add SMLoc to expressionsFangrui Song1-3/+4
2025-07-04MCParser: Add SMLoc to expressionsFangrui Song1-1/+1
2025-07-03[RISCV] Add SF_ to SiFive instructions in RISCVGenInstrInfo.inc. NFC (#146939)Craig Topper1-3/+3
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa1-0/+4
2025-07-01[RISCV][MC] Support Base P non-GPR pair instructions (#137927)realqhc1-0/+9
2025-06-28MCExpr: Migrate away from operator<<Fangrui Song1-2/+3
2025-06-28MCParsedAsmOperand::print: Add MCAsmInfo parameterFangrui Song1-1/+1
2025-06-23[RISCV] Make All VType Parts Optional (#144971)Sam Elliott1-64/+65
2025-06-23[RISCV][NFC] Remove hasStdExtCOrZca (#145139)Sam Elliott1-4/+2
2025-06-20[RISCV] Add symbol parsing support for XAndesPerf branch instructions (#137748)Jim Lin1-5/+1
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-06-15RISCV: Replace RISCVMCExpr with MCSpecifierExprFangrui Song1-24/+22
2025-06-15RISCV: Move RISCVMCExpr functions to RISCVMCAsmInfo or RISCVMCAsmBackendFangrui Song1-3/+3
2025-06-15RISCV: Rename RISCVMCExpr::VK_ to RISCV::S_Fangrui Song1-22/+21
2025-05-27MCSymbol: Remove the default argument of getVariableValueFangrui Song1-3/+2
2025-05-25Replace #include MCAsmLexer.h with AsmLexer.hFangrui Song1-1/+1
2025-05-23RISCV: Remove shouldForceRelocation and unneeded relocationsFangrui Song1-15/+0
2025-05-21[RISCV] Add MC layer support for XSfmm*. (#133031)Craig Topper1-0/+65
2025-05-17RISCV: Replace most Specifier constants with relocation typesFangrui Song1-18/+17
2025-05-15[RISCV][MC] Add support for Q extension (#139369)Iris Shi1-2/+20
2025-04-28[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)Jim Lin1-0/+39
2025-04-21[RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (#136552)Liao Chunyu1-18/+0
2025-04-17Recommit "[RISCV] Strengthen register usage validation for XTheadMemPair load...Iris1-2/+2
2025-04-17Revert "[RISCV] Strengthen register usage validation for XTheadMemPair loads ...Fangrui Song1-2/+2
2025-04-17[RISCV] Move checking for constant 3/4 for XTHeadMemPair to the instruction m...Craig Topper1-13/+8
2025-04-18[RISCV] Strengthen register usage validation for XTheadMemPair loads (#136241)Iris1-2/+2
2025-04-17[RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#...Craig Topper1-6/+9
generated by cgit v1.2.3 (git 2.39.1) at 2026-05-16 04:43:34 +0000