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path: root/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2023-02-17Simplify with hasFeature. NFCFangrui Song1-2/+2
2023-02-02[PowerPC] Switch to by-name matching for instructions (part 2 of 2).James Y Knight1-126/+19
2023-02-02[PowerPC] Don't crash when disassembling invalid immediateNemanja Ivanovic1-2/+4
2023-01-28[Target] Use llvm::count{l,r}_{zero,one} (NFC)Kazu Hirata1-1/+1
2022-11-03[PowerPC] Add new DMR register classes to Future CPU.Stefan Pintilie1-1/+40
2022-05-15Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`Sheng1-1/+1
2022-03-25[Disassember][NFCI] Use strong type for instruction decoderMaksim Panchenko1-43/+53
2021-10-08Move TargetRegistry.(h|cpp) from Support to MCReid Kleckner1-1/+1
2021-06-15[PowerPC] Export 16 byte load-store instructionsKai Luo1-0/+6
2021-04-15[PowerPC] Add ROP Protection Instructions for PowerPCStefan Pintilie1-0/+17
2021-04-09Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"Mitch Phillips1-17/+0
2021-04-09[PowerPC] Add ROP Protection Instructions for PowerPCStefan Pintilie1-0/+17
2021-01-02[PowerPC] Add the LLVM triple for powerpcle [1/5]Brandon Bergren1-0/+2
2020-09-30[PowerPC] Add outer product instructions for MMAAhsan Saghir1-0/+9
2020-09-25[PowerPC] Add accumulator register class and instructionsBaptiste Saleil1-0/+6
2020-09-21[PowerPC] Add vector pair load/store instructions and vector pair register classBaptiste Saleil1-0/+6
2020-07-28Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"Jinsong Ji1-13/+2
2020-07-27Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"Jinsong Ji1-2/+13
2020-07-27[PowerPC] Remove QPX/A2Q BGQ/BGP CNK supportJinsong Ji1-13/+2
2020-04-01[PPCInstPrinter] Change B to print the target address in hexadecimal formFangrui Song1-3/+3
2020-03-31[PPCInstPrinter] Print conditional branches as `bt 2, $target` instead of `bt...Fangrui Song1-0/+7
2020-01-28[PowerPC][Future] Add pld and pstd to future CPUVictor Huang1-0/+29
2020-01-24[PowerPC][Future] Add prefixed instruction paddi to future CPUVictor Huang1-2/+32
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2020-01-11[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song1-3/+1
2019-09-12[PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC re...Craig Topper1-6/+0
2019-06-27[PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and othersJinsong Ji1-6/+0
2019-06-11Revert CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-06-10CMake: Make most target symbols hidden by defaultTom Stellard1-1/+1
2019-05-15[PowerPC] Create a TargetInfo header. NFCRichard Trieu1-0/+1
2019-02-12[PowerPC] Fix printing of negative offsets in call instruction dissasembly.Sean Fertile1-0/+8
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-12-29[PowerPC][NFC] Macro for register set defs for the Asm ParserNemanja Ivanovic1-191/+18
2018-09-10[Target] Untangle disassemblersBenjamin Kramer1-1/+1
2018-07-18Introduce codegen for the Signal Processing EngineJustin Hibbits1-0/+23
2018-07-18Complete the SPE instruction set patternsJustin Hibbits1-0/+50
2017-05-11[PPC] Change the register constraint of the first source operand of instructi...Guozhi Wei1-0/+17
2016-10-09Move the global variables representing each Target behind accessor functionMehdi Amini1-3/+3
2016-10-04[Power9] Part-word VSX integer scalar loads/stores and sign extend instructionsNemanja Ivanovic1-8/+25
2016-04-28This reverts commit r265505.Kit Barton1-6/+0
2016-04-06[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random nu...Chuang-Yu Cheng1-0/+6
2016-03-08[Power9] Implement new vsx instructions: load, store instructions for vector ...Kit Barton1-0/+15
2016-01-26Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer1-1/+1
2015-08-11Explicitly clear the MI operand list when getInstruction() is called. Call M...Cameron Esfahani1-2/+0
2015-07-15[PPC] Disassemble little endian ppc instructions in the right byte orderBenjamin Kramer1-8/+17
2015-05-26Use std::bitset for SubtargetFeatures.Michael Kuperstein1-1/+1
2015-05-13MC: Modernize MCOperand API naming. NFC.Jim Grosbach1-12/+12
2015-05-13Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein1-1/+1
2015-05-13Use std::bitset for SubtargetFeaturesMichael Kuperstein1-1/+1
2015-05-07Add VSX Scalar loads and stores to the PPC back endNemanja Ivanovic1-0/+26
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