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author | Sean Fertile <sfertile@ca.ibm.com> | 2019-02-12 17:48:22 +0000 |
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committer | Sean Fertile <sfertile@ca.ibm.com> | 2019-02-12 17:48:22 +0000 |
commit | c069452027267151f7edc699de1295830204539e (patch) | |
tree | 5f8ccde0cc19ffb4f6d015e3d46dfb37580ddda2 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
parent | acbb7ca26c657446124b117c1af7bfaaa524c0a3 (diff) | |
download | llvm-c069452027267151f7edc699de1295830204539e.zip llvm-c069452027267151f7edc699de1295830204539e.tar.gz llvm-c069452027267151f7edc699de1295830204539e.tar.bz2 |
[PowerPC] Fix printing of negative offsets in call instruction dissasembly.
llvm-svn: 353865
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 8f96951..9fb37c5 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -60,6 +60,14 @@ extern "C" void LLVMInitializePowerPCDisassembler() { createPPCLEDisassembler); } +static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, + uint64_t Addr, + const void *Decoder) { + int32_t Offset = SignExtend32<24>(Imm); + Inst.addOperand(MCOperand::createImm(Offset)); + return MCDisassembler::Success; +} + // FIXME: These can be generated by TableGen from the existing register // encoding values! |