Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"

This reverts commit 16fe741c69429235210c03c46420f8fa6aece4a1.

Reason: Broke the UBSan buildbots. More information available in the
phabricator review: https://reviews.llvm.org/D99375

1 files changed, 0 insertions, 17 deletions

diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 706f6df4..3e9286f 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -279,23 +279,6 @@ static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
-                                            int64_t Address,
-                                            const void *Decoder) {
-  // Decode the memrix field for a hash store or hash check operation.
-  // The field is composed of a register and an immediate value that is 6 bits
-  // and covers the range -8 to -512. The immediate is always negative and 2s
-  // complement which is why we sign extend a 7 bit value.
-  const uint64_t Base = Imm >> 6;
-  const uint64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) << 3;
-
-  assert(Base < 32 && "Invalid base register");
-
-  Inst.addOperand(MCOperand::createImm(Disp));
-  Inst.addOperand(MCOperand::createReg(RRegs[Base]));
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
                                          int64_t Address, const void *Decoder) {
   // Decode the memrix16 field (imm, reg), which has the low 12-bits as the