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AgeCommit message (Expand)AuthorFilesLines
7 days[Mips] Add r5900 (PlayStation 2 Emotion Engine) CPU support (#176666)Rick Gaiser11-102/+279
7 days[MIPS][ISel] Fix musttail (#161860)Djordje Todorovic2-24/+36
12 days[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)Sam Elliott6-14/+17
2026-01-19FastISel: Thread LibcallLoweringInfo through (#176799)Matt Arsenault3-11/+18
2026-01-19[X86][WinEH] Insert nop after unwinding inline assembly (#176393)Nikita Popov2-2/+4
2026-01-13[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subr...Christudasan Devadasan1-1/+1
2026-01-11[TargetLowering] Change the `softPromoteHalfType` default to `true` (#175149)Trevor Gross1-2/+0
2026-01-08[Mips] Add MipsPat `(MipsGPRel tglobaladdr:$in)` to select MipsISD::GPRel Tar...yingopq1-0/+3
2026-01-08MIPS: expandDivRem add a NOP after BNE (#174908)YunQiang Su1-0/+1
2026-01-04[NFC] Delete unnecessary apostrophe at the end of its (#173974)willmafh2-2/+2
2025-12-26[Mips] Add support for Mips::GPR64Idx in MipsRegisterBankInfo (#173534)yingopq4-68/+78
2025-12-26MIPSr6: Set FSELECT Legal for f64 (#173591)YunQiang Su8-68/+186
2025-12-26[Mips] Mark function calls as possibly changing FCSR (FCR31) (#170314)Erik Enikeev2-0/+7
2025-12-26MIPSr6: Set SETCC CondCode not supported by hardware to Expand (#173541)YunQiang Su3-13/+13
2025-12-23Mips: Improve MipsAsmParser::expandDivRem (#172967)YunQiang Su3-56/+20
2025-12-18[mips][micromips] Add mayRaiseFPException to appropriate instructions, mark a...Erik Enikeev5-345/+405
2025-12-16[CodeGen] expand-fp: Change frem expansion criterion (#158285)Frederik Harwath1-2/+2
2025-12-16[Mips] Use getSigned() for LwConstant32 immedateNikita Popov1-1/+1
2025-12-12[Mips] Add compact branch patterns for MipsR6 (#171131)ArielCPU6-19/+111
2025-12-12[Mips] Support "$sp" named register (#171793)yingopq2-12/+92
2025-12-09Revert "[Mips] Support "$sp" named register (#136821)"YunQiang Su2-92/+12
2025-12-09[Mips] Support "$sp" named register (#136821)yingopq2-12/+92
2025-12-05[Mips] TableGen-erate SDNode descriptions (#168307)Sergei Barannikov11-418/+176
2025-11-26CodeGen: Make all targets override pseudos with pointers (#159881)Matt Arsenault1-0/+2
2025-11-25CodeGen: Move libcall lowering configuration to subtarget (#168621)Matt Arsenault4-36/+38
2025-11-25[Mips] Set custom lowering for STRICT_FSETCC/STRICT_FSETCCS ops. (#168303)Erik Enikeev2-1/+29
2025-11-24[Mips] Add instruction selection for strict FP (#168870)Erik Enikeev4-36/+64
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault1-1/+1
2025-11-18Mips: Remove manual libcall name search and table (#168595)Matt Arsenault1-67/+32
2025-11-12[Mips] Remove implicit conversions of MCRegister to unsigned. NFC (#167645)Craig Topper6-183/+184
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault6-67/+57
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault1-2/+2
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault6-16/+13
2025-11-09[Target] Fix misleading indentation (NFC) (#167206)Kazu Hirata1-2/+2
2025-11-04[llvm] Use conventional enum declarations (NFC) (#166318)Kazu Hirata1-1/+1
2025-11-02[ADT] Prepare to deprecate variadic `StringSwitch::Cases`. NFC. (#166020)Jakub Kuderski1-1/+1
2025-10-25[Target] Add "override" where appropriate (NFC) (#165083)Kazu Hirata1-1/+1
2025-10-16[llvm] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163702)Kazu Hirata2-6/+8
2025-10-11[ARM][TargetLowering] Combine Level should not be a factor in shouldFoldConst...AZero132-3/+2
2025-10-10[Mips] Fix clang crashes when assembling invalid MIPS beql instructions with ...yingopq2-4/+14
2025-09-28[MIPS][float] Fixed SingleFloat codegen on N32/N64 targets (#140575)Davide Mor4-23/+72
2025-09-25[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips...yingopq1-26/+191
2025-09-23[NFC][MC][CodeEmitterGen] Extract error reporting into a helper function (#15...Rahul Joshi1-1/+0
2025-09-19Mips: Switch to RegClassByHwMode (#158273)Matt Arsenault8-48/+80
2025-09-18Revert "[Mips] Fix atomic min/max generate mips4 instructions when compiling ...yingopq1-188/+25
2025-09-17[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips...yingopq1-25/+188
2025-09-16[Mips] Fix inst `sc` disassemble assert when configured -mattr=+ptr64 (#158253)yingopq1-1/+1
2025-09-14[Mips] Remove `size` operand of LwRxPcTcp16 / LwRxPcTcpX16 (#157348)Sergei Barannikov2-3/+3
2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault1-2/+2
2025-09-12CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)Matt Arsenault8-17/+19
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