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path: root/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
AgeCommit message (Expand)AuthorFilesLines
2020-01-14[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-10/+17
2020-01-10Reverting, broke some bots. Need further investigation.Diogo Sampaio1-17/+10
2020-01-10[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio1-10/+17
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-16/+16
2019-04-04[IR] Refactor attribute methods in Function class (NFC)Evandro Menezes1-1/+1
2019-03-25[ARM] Add missing memory operands to a bunch of instructions.Eli Friedman1-20/+46
2019-02-26[ARM] Be super conservative about atomicsPhilip Reames1-2/+5
2019-02-11[ARM] LoadStoreOptimizer: reoder limitSjoerd Meijer1-1/+6
2019-02-11[ARM] LoadStoreOptimizer: just a clean-up. NFC.Sjoerd Meijer1-35/+25
2019-02-08[ARM] Add OptMinSize to ARMSubtargetSam Parker1-1/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-09-27llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song1-8/+7
2018-09-24[ARM][ARMLoadStoreOptimizer]Luke Cheeseman1-0/+14
2018-08-16[MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth1-4/+4
2018-07-30Remove trailing spaceFangrui Song1-1/+1
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen1-2/+2
2018-05-09[DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen1-8/+8
2018-04-05[ARM] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang1-8/+8
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun1-5/+5
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih1-1/+1
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih1-1/+1
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-3/+3
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie1-3/+3
2017-11-03Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie1-1/+1
2017-09-28ARM: Fix cases where CSI Restored bit is not clearedMatthias Braun1-0/+11
2017-09-20[ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnin...Eugene Zelenko1-25/+58
2017-08-28Fix ARMv4 supportJoerg Sonnenberger1-0/+1
2017-08-28[ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing.Geoff Berry1-30/+19
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-03-17[ARM] Use alias analysis in ARMPreAllocLoadStoreOpt.Eli Friedman1-16/+14
2017-03-02[ARM] Fix insert point for store rescheduling.Eli Friedman1-12/+19
2017-03-02Revert r296708; causing test failures on ARM hosts.Eli Friedman1-18/+12
2017-03-01[ARM] Fix insert point for store rescheduling.Eli Friedman1-12/+18
2017-03-01[ARM] Check correct instructions for load/store rescheduling.Eli Friedman1-1/+1
2017-02-28[ARM] Don't generate deprecated T1 STM.Eli Friedman1-4/+3
2017-01-20[ARM] Use helpers for adding pred / CC operands. NFCDiana Picus1-16/+28
2017-01-13[ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFCDiana Picus1-9/+18
2017-01-13[CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus1-6/+4
2017-01-13[ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus1-2/+3
2016-12-08LivePhysReg: Use reference instead of pointer in init(); NFCMatthias Braun1-1/+1
2016-10-01Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini1-4/+2
2016-08-26Handle empty functions with debug info in load/store opt passPablo Barrio1-1/+1
2016-08-25MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compu...Matthias Braun1-1/+1
2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer1-1/+1
2016-07-16ARM: Initialize LoadStore passes in TargetMachineMatthias Braun1-16/+5
2016-07-08ARM: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith1-46/+46
2016-07-06[ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCIDiana Picus1-1/+1
2016-06-12Pass DebugLoc and SDLoc by const ref.Benjamin Kramer1-30/+33
2016-06-07[ARM] Transform LDMs into writeback form to save code sizeJames Molloy1-3/+23
2016-05-03livePhysRegs: Pass MBB by reference in addLive{Ins|Outs}(); NFCMatthias Braun1-1/+1
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