diff options
| author | Diana Picus <diana.picus@linaro.org> | 2017-01-13 10:37:37 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-01-13 10:37:37 +0000 |
| commit | a2c59149e14b52b613a5403302cf84d6ab0456d0 (patch) | |
| tree | f7470e3585f1228eb055e2ebcef28908bef10351 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 8a73f5562f9e7ce0c9416fbd0d8d2dc8f1807898 (diff) | |
| download | llvm-a2c59149e14b52b613a5403302cf84d6ab0456d0.zip llvm-a2c59149e14b52b613a5403302cf84d6ab0456d0.tar.gz llvm-a2c59149e14b52b613a5403302cf84d6ab0456d0.tar.bz2 | |
[ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFC
For AddDefaultT1CC, we add a new helper t1CondCodeOp, which creates the
appropriate register operand. For AddNoT1CC, we use the existing condCodeOp
helper - we only had two uses of AddNoT1CC, so at this point it's probably not
worth having yet another helper just for them.
Differential Revision: https://reviews.llvm.org/D28603
llvm-svn: 291894
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 1bfcb72..1dd4c9e 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -517,8 +517,12 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, if (InsertSub) { // An instruction above couldn't be updated, so insert a sub. - AddDefaultT1CC(BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true) - .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); + BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) + .add(t1CondCodeOp(true)) + .addReg(Base) + .addImm(WordOffset * 4) + .addImm(Pred) + .addReg(PredReg); return; } @@ -534,9 +538,12 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, // information and *always* have to reset at the end of a block. // See PR21029. if (MBBI != MBB.end()) --MBBI; - AddDefaultT1CC( - BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true) - .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); + BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) + .add(t1CondCodeOp(true)) + .addReg(Base) + .addImm(WordOffset * 4) + .addImm(Pred) + .addReg(PredReg); } } @@ -713,10 +720,12 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti( .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4) .addImm(Pred).addReg(PredReg); } else - AddDefaultT1CC( - BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase), true) - .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) - .addImm(Pred).addReg(PredReg); + BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) + .add(t1CondCodeOp(true)) + .addReg(Base, getKillRegState(KillOldBase)) + .addImm(Offset) + .addImm(Pred) + .addReg(PredReg); } else { BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) |