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| author | Diogo Sampaio <diogo.sampaio@arm.com> | 2020-01-10 13:32:02 +0000 |
|---|---|---|
| committer | Diogo Sampaio <diogo.sampaio@arm.com> | 2020-01-10 13:40:41 +0000 |
| commit | b1bb5ce96d349689085eab38121c85737de1fcaa (patch) | |
| tree | 34941706891c7cb54d3ab83d977ae59a4e5306e6 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | b3af8ab7f83c2a825c584ddedf5cc9207ca66b44 (diff) | |
| download | llvm-b1bb5ce96d349689085eab38121c85737de1fcaa.zip llvm-b1bb5ce96d349689085eab38121c85737de1fcaa.tar.gz llvm-b1bb5ce96d349689085eab38121c85737de1fcaa.tar.bz2 | |
Reverting, broke some bots. Need further investigation.
Summary: This reverts commit 8c12769f3046029e2a9b4e48e1645b1a77d28650.
Reviewers:
Subscribers:
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 27 |
1 files changed, 10 insertions, 17 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 12dddd2..4a193fe 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -696,23 +696,18 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti( return nullptr; } - int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm - : ARM::t2ADDri) - : (isThumb1 && Base == ARM::SP) - ? ARM::tADDrSPi - : (isThumb1 && Offset < 8) - ? ARM::tADDi3 - : isThumb1 ? ARM::tADDi8 : ARM::ADDri; + int BaseOpc = + isThumb2 ? ARM::t2ADDri : + (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : + (isThumb1 && Offset < 8) ? ARM::tADDi3 : + isThumb1 ? ARM::tADDi8 : ARM::ADDri; if (Offset < 0) { - // FIXME: There are no Thumb1 load/store instructions with negative - // offsets. So the Base != ARM::SP might be unnecessary. - Offset = -Offset; - BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm - : ARM::t2SUBri) - : (isThumb1 && Offset < 8 && Base != ARM::SP) - ? ARM::tSUBi3 - : isThumb1 ? ARM::tSUBi8 : ARM::SUBri; + Offset = - Offset; + BaseOpc = + isThumb2 ? ARM::t2SUBri : + (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 : + isThumb1 ? ARM::tSUBi8 : ARM::SUBri; } if (!TL->isLegalAddImmediate(Offset)) @@ -1191,10 +1186,8 @@ static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg, case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break; case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break; case ARM::t2SUBri: - case ARM::t2SUBspImm: case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break; case ARM::t2ADDri: - case ARM::t2ADDspImm: case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break; case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break; |