diff options
| author | Eli Friedman <efriedma@codeaurora.org> | 2017-02-28 23:32:55 +0000 |
|---|---|---|
| committer | Eli Friedman <efriedma@codeaurora.org> | 2017-02-28 23:32:55 +0000 |
| commit | 36795239f57337f56b840a254d6b69cdcf918101 (patch) | |
| tree | a0253d40e96566559471ef66e68daf67433ab572 /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 33fd0bbbe8b2d5dd98964877d4f4344633e3197b (diff) | |
| download | llvm-36795239f57337f56b840a254d6b69cdcf918101.zip llvm-36795239f57337f56b840a254d6b69cdcf918101.tar.gz llvm-36795239f57337f56b840a254d6b69cdcf918101.tar.bz2 | |
[ARM] Don't generate deprecated T1 STM.
This prevents generating stm r1!, {r0, r1} on Thumb1, where value
stored for r1 is UNKONWN.
Patch by Zhaoshi Zheng.
Differential Revision: https://reviews.llvm.org/D27910
llvm-svn: 296538
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index c87f703..8e51f13 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -609,13 +609,12 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti( // Exception: If the base register is in the input reglist, Thumb1 LDM is // non-writeback. // It's also not possible to merge an STR of the base register in Thumb1. - if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) { + if (isThumb1 && ContainsReg(Regs, Base)) { assert(Base != ARM::SP && "Thumb1 does not allow SP in register list"); - if (Opcode == ARM::tLDRi) { + if (Opcode == ARM::tLDRi) Writeback = false; - } else if (Opcode == ARM::tSTRi) { + else if (Opcode == ARM::tSTRi) return nullptr; - } } ARM_AM::AMSubMode Mode = ARM_AM::ia; |