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path: root/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
2017-12-22[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky1-5/+30
2017-12-13AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault1-1/+41
2017-12-11[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky1-14/+42
2017-11-20[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky1-0/+3
2017-08-10[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko1-13/+28
2017-08-09[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky1-0/+3
2017-07-21AMDGPU: Add instruction definitions for some scratch_* instructionsMatt Arsenault1-0/+7
2017-07-18[AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8Dmitry Preobrazhensky1-0/+5
2017-06-27[AMDGPU] SDWA: several fixes for V_CVT and VOPC instructionsSam Kolton1-1/+3
2017-06-21[AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky1-2/+0
2017-06-21[AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton1-30/+68
2017-06-07Move Object format code to lib/BinaryFormat.Zachary Turner1-1/+1
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-3/+2
2017-05-26[AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton1-20/+73
2017-05-19[AMDGPU][MC] Corrected disassembler to decode instructions with 2 literalsDmitry Preobrazhensky1-4/+10
2017-04-10AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault1-4/+12
2017-02-27AMDGPU: Add VOP3P instruction formatMatt Arsenault1-0/+17
2017-02-18AMDGPU: Fix disassembly of aperture registersMatt Arsenault1-0/+5
2017-02-15AMDGPU: Replace assert with report_fatal_errorMatt Arsenault1-1/+2
2016-12-10AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault1-25/+119
2016-11-29AMDGPU: Disallow exec as SMEM instruction operandMatt Arsenault1-4/+9
2016-11-15AMDGPU: Replace assert(false) with unreachableMatt Arsenault1-3/+11
2016-11-01AMDGPU: Whitespace fixesMatt Arsenault1-3/+3
2016-10-09Move the global variables representing each Target behind accessor functionMehdi Amini1-2/+4
2016-10-06[AMDGPU] Disassembler: print label names in branch instructionsSam Kolton1-0/+58
2016-09-26Revert "[AMDGPU] Disassembler: print label names in branch instructions"Sam Kolton1-58/+0
2016-09-26[AMDGPU] Disassembler: print label names in branch instructionsSam Kolton1-0/+58
2016-07-19AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault1-0/+5
2016-06-10AMDGPU: Fix trailing whitespaceMatt Arsenault1-1/+1
2016-06-09[AMDGPU] Disassembler: Support for sdwa instructionsSam Kolton1-1/+5
2016-05-26Fix build warning introduced in r270552 "[AMDGPU][llvm-mc] Disassembler: supp...Artem Tamazov1-1/+2
2016-05-24[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.Artem Tamazov1-42/+82
2016-04-29Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rewor...Artem Tamazov1-5/+6
2016-04-27Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ...Chad Rosier1-6/+0
2016-04-27[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov1-0/+6
2016-03-31[AMDGPU] Disassembler: support for DPPSam Kolton1-7/+19
2016-03-10[AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin1-0/+2
2016-03-04test commitValery Pykhtin1-1/+1
2016-03-01[AMDGPU] Remove unused disassembler code.Nikolay Haustov1-2/+0
2016-03-01[AMDGPU] Fix build warnings.Nikolay Haustov1-2/+2
2016-03-01[AMDGPU] Disassembler code refactored + error messages.Nikolay Haustov1-346/+266
2016-02-25[AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov1-49/+206
2016-02-18[AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard1-0/+302
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