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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 15:36:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-21 15:36:16 +0000 |
| commit | ca7b0a17775cdfab49cffda451802ebb2b6bc120 (patch) | |
| tree | 29e2e60049760654e11f6543fdaa9e024bc599a4 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | cd4c977b8b998a078f5416c8d71bc5b552a6df2d (diff) | |
| download | llvm-ca7b0a17775cdfab49cffda451802ebb2b6bc120.zip llvm-ca7b0a17775cdfab49cffda451802ebb2b6bc120.tar.gz llvm-ca7b0a17775cdfab49cffda451802ebb2b6bc120.tar.bz2 | |
AMDGPU: Add instruction definitions for some scratch_* instructions
Omit atomics for now since they probably aren't useful.
llvm-svn: 308747
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 966c6fe..ca4e501 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -95,6 +95,7 @@ DECODE_OPERAND_REG(VReg_128) DECODE_OPERAND_REG(SReg_32) DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) +DECODE_OPERAND_REG(SReg_32_XEXEC_HI) DECODE_OPERAND_REG(SReg_64) DECODE_OPERAND_REG(SReg_64_XEXEC) DECODE_OPERAND_REG(SReg_128) @@ -365,6 +366,12 @@ MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( return decodeOperand_SReg_32(Val); } +MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( + unsigned Val) const { + // SReg_32_XM0 is SReg_32 without EXEC_HI + return decodeOperand_SReg_32(Val); +} + MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { return decodeSrcOp(OPW64, Val); } |