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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-07-18 13:12:48 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2017-07-18 13:12:48 +0000 |
| commit | 30fc523984dec81232167e07d8fc25c92e8562f7 (patch) | |
| tree | fbfdd8847cbc2df4f4cabb290e4afc5837b84747 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 4793a11df958f376e71e1c868d897323de54a96e (diff) | |
| download | llvm-30fc523984dec81232167e07d8fc25c92e8562f7.zip llvm-30fc523984dec81232167e07d8fc25c92e8562f7.tar.gz llvm-30fc523984dec81232167e07d8fc25c92e8562f7.tar.bz2 | |
[AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8
See Bug 33639: https://bugs.llvm.org//show_bug.cgi?id=33639
Reviewers: vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D34892
llvm-svn: 308303
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index f26e492..966c6fe 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -87,6 +87,7 @@ DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) DECODE_OPERAND_REG(VGPR_32) DECODE_OPERAND_REG(VS_32) DECODE_OPERAND_REG(VS_64) +DECODE_OPERAND_REG(VS_128) DECODE_OPERAND_REG(VReg_64) DECODE_OPERAND_REG(VReg_96) @@ -318,6 +319,10 @@ MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { return decodeSrcOp(OPW64, Val); } +MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { + return decodeSrcOp(OPW128, Val); +} + MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { return decodeSrcOp(OPW16, Val); } |