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| author | Chad Rosier <mcrosier@codeaurora.org> | 2016-04-27 18:29:11 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2016-04-27 18:29:11 +0000 |
| commit | 03e1647d19647e6c45688f791e26d7a09b62577c (patch) | |
| tree | 4530cf336103b2188b17081c375d39ff27cf2acd /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 622b95be7b0b49e6e428cff3bc7759bc544994aa (diff) | |
| download | llvm-03e1647d19647e6c45688f791e26d7a09b62577c.zip llvm-03e1647d19647e6c45688f791e26d7a09b62577c.tar.gz llvm-03e1647d19647e6c45688f791e26d7a09b62577c.tar.bz2 | |
Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."
This reverts commit r267733 due to a -Werror,-Wunused-function error.
llvm-svn: 267752
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index bbec73f..2990b57 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -68,7 +68,6 @@ DECODE_OPERAND(VReg_128) DECODE_OPERAND(SGPR_32) DECODE_OPERAND(SReg_32) -DECODE_OPERAND(SReg_32_XM0) DECODE_OPERAND(SReg_64) DECODE_OPERAND(SReg_128) DECODE_OPERAND(SReg_256) @@ -249,11 +248,6 @@ MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { return decodeSrcOp(OP32, Val); } -MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const { - // SReg_32_XM0 is SReg_32 without M0 - return decodeOperand_SReg_32(Val); -} - MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { // see decodeOperand_SReg_32 comment return decodeSrcOp(OP64, Val); |