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path: root/llvm/lib/CodeGen/CodeGen.cpp
AgeCommit message (Expand)AuthorFilesLines
2022-05-19[SelectOpti][1/5] Setup new select-optimize passSotiris Apostolakis1-0/+1
2022-04-11[CodeGen] Async unwind - add a pass to fix CFI informationMomchil Velikov1-0/+1
2022-04-05Revert "[CodeGen] Async unwind - add a pass to fix CFI information"Muhammad Omair Javaid1-1/+0
2022-04-04[CodeGen] Async unwind - add a pass to fix CFI informationMomchil Velikov1-0/+1
2022-03-23Reland "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO"Julian Lettner1-0/+1
2022-03-23Revert "Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO"Zequan Wu1-1/+0
2022-03-17Lower `@llvm.global_dtors` using `__cxa_atexit` on MachOJulian Lettner1-0/+1
2022-03-15Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors`...Simon Pilgrim1-1/+0
2022-03-14Lower `@llvm.global_dtors` using `__cxa_atexit` on MachOJulian Lettner1-0/+1
2022-02-10Reland "[clang-cl] Support the /JMC flag"Yuanfang Chen1-0/+1
2022-02-10Revert "[clang-cl] Support the /JMC flag"Yuanfang Chen1-1/+0
2022-02-10[clang-cl] Support the /JMC flagYuanfang Chen1-0/+1
2021-12-10Reapply CycleInfo: Introduce cycles as a generalization of loopsSameer Sahasrabuddhe1-0/+2
2021-12-07Revert "CycleInfo: Introduce cycles as a generalization of loops"Jonas Devlieghere1-2/+0
2021-12-07CycleInfo: Introduce cycles as a generalization of loopsSameer Sahasrabuddhe1-0/+2
2021-11-23[SampleFDO] Recompute BFI if the sample loader changes BPIRong Xu1-0/+2
2021-07-14[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEsDjordje Todorovic1-0/+1
2021-07-07[AMDGPU] Disable garbage collection passesStanislav Mekhanoshin1-0/+1
2021-01-02[NFC][CodeGen] Split DwarfEHPrepare pass into an actual transform and an lega...Roman Lebedev1-1/+1
2020-12-16[Debugify] Support checking Machine IR debug infoXiang1 Zhang1-0/+1
2020-12-16Revert "[Debugify] Support checking Machine IR debug info"Xiang1 Zhang1-1/+0
2020-12-16[Debugify] Support checking Machine IR debug infoXiang1 Zhang1-0/+1
2020-12-14Revert "[Debugify] Support checking Machine IR debug info"Nico Weber1-1/+0
2020-12-14[Debugify] Support checking Machine IR debug infoXiang1 Zhang1-0/+1
2020-12-14Revert "[Debugify] Support checking Machine IR debug info"Xiang1 Zhang1-1/+0
2020-12-14[Debugify] Support checking Machine IR debug infoXiang1 Zhang1-0/+1
2020-12-08[ScalarizeMaskedMemIntrinsic] Move from CodeGen into TransformsAnna Thomas1-1/+0
2020-08-06[NFC] Rename BBSectionsPrepare -> BasicBlockSections.Snehasish Kumar1-1/+1
2020-04-10Re-land [Codegen/Statepoint] Allow usage of registers for non gc deopt values.Serguei Katkov1-0/+1
2020-04-09Add pass to strip debug info from MIRDaniel Sanders1-0/+1
2020-04-09Revert "[Codegen/Statepoint] Allow usage of registers for non gc deopt values."Serguei Katkov1-1/+0
2020-04-09[Codegen/Statepoint] Allow usage of registers for non gc deopt values.Serguei Katkov1-0/+1
2020-04-07Add MIR-level debugify with only locations support for nowDaniel Sanders1-0/+1
2020-03-16Basic Block Sections support in LLVM.Sriraman Tallam1-0/+1
2020-03-10[VE] Target-specific bit size for sjljehprepareKazushi (Jam) Marukawa1-0/+1
2019-12-03[CodeGen] Move ARMCodegenPrepare to TypePromotionSam Parker1-0/+1
2019-10-28Add Windows Control Flow Guard checks (/guard:cf).Andrew Paverd1-0/+1
2019-09-30[NewPM] Port MachineModuleInfo to the new pass manager.Yuanfang Chen1-1/+1
2019-09-10Revert "Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen...Dmitri Gribenko1-0/+1
2019-09-10Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into op...Clement Courbet1-1/+0
2019-09-05[MIR] MIRNamer pass for improving MIR test authoring experience.Puyan Lotfi1-0/+1
2019-09-03[MachinePipeliner] Add a way to unit-test the schedule emitterJames Molloy1-0/+1
2019-08-20 [CodeGen] Add a pass to do block predication on SSA machine IR.Thomas Raoux1-0/+1
2019-06-26Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into op...Clement Courbet1-0/+1
2019-06-26[ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.Clement Courbet1-1/+0
2019-06-19Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault1-1/+1
2019-06-07[CodeGen] Generic Hardware Loop SupportSam Parker1-0/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-11-19Subject: [PATCH] [CodeGen] Add pass to combine interleaved loads.Martin Elshuber1-0/+1
2018-07-26RegUsageInfo: Cleanup; NFCMatthias Braun1-0/+2
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