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authorXiang1 Zhang <xiang1.zhang@intel.com>2020-12-14 23:48:11 -0800
committerXiang1 Zhang <xiang1.zhang@intel.com>2020-12-16 18:04:05 -0800
commit50aaa8c274910d78d7bf6c929a34fe58b1f45579 (patch)
treeaaa47393426c0bfc99eb49de4415ccbb746b21fb /llvm/lib/CodeGen/CodeGen.cpp
parent2e6e4e6aeef71dd8fba038177a34a82b574d2126 (diff)
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[Debugify] Support checking Machine IR debug info
Add mir-check-debug pass to check MIR-level debug info. For IR-level, currently, LLVM have debugify + check-debugify to generate and check debug IR. Much like the IR-level pass debugify, mir-debugify inserts sequentially increasing line locations to each MachineInstr in a Module, But there is no equivalent MIR-level check-debugify pass, So now we support it at "mir-check-debug". Reviewed By: djtodoro Differential Revision: https://reviews.llvm.org/D91595
Diffstat (limited to 'llvm/lib/CodeGen/CodeGen.cpp')
-rw-r--r--llvm/lib/CodeGen/CodeGen.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 92a2b73..9492549 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -25,6 +25,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeBranchRelaxationPass(Registry);
initializeCFGuardLongjmpPass(Registry);
initializeCFIInstrInserterPass(Registry);
+ initializeCheckDebugMachineModulePass(Registry);
initializeCodeGenPreparePass(Registry);
initializeDeadMachineInstructionElimPass(Registry);
initializeDebugifyMachineModulePass(Registry);