aboutsummaryrefslogtreecommitdiff
path: root/sim/riscv
AgeCommit message (Collapse)AuthorFilesLines
2023-10-18sim/riscv: fix JALR instruction simulationJaydeep Patil1-1/+1
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
Add explicit arch-specific modules.c rules to keep the build from generating an incorrect common/modules.c. Otherwise the pattern rules would cascade such that it'd look for $arch/modules.o which turned into common/modules.c which triggered the gen rule. My local testing of this code didn't catch this bug because of how Automake manages .Po (dependency files) in incremental builds -- it was adding extra rules that override the pattern rules which caused the build to generate correct modules.c files. But when building from a cold cache, the pattern rules would force common/modules.c to be used leading to crashes at runtime.
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
This makes sure the arch-specific modules.c wildcard is matched and not the common/%.c so that we compile it correctly. It also makes sure each subdir has depdir logic enabled.
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
This simplifies the build logic and avoids an Automake bug where the common_libcommon_a_OBJECTS variable isn't set in the arch libsim.a DEPENDENCIES for targets that, alphabetically, come before "common". We aren't affected by that bug with the current code, but as we move things out of SIM_ALL_RECURSIVE_DEPS and rely on finer dependencies, we will trip over it.
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-22/+0
These aren't used anymore, so punt them all.
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: riscv: move arch-specific file compilation to top-levelMike Frysinger1-3/+2
The arch-specific compiler flags are duplicated, but they'll be cleaned up once we move all subdir compiles to the top-level.
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-2/+0
Now that all ports have moved to creating libsim.a in the top-level, drop all the support code to create it in a subdir.
2023-01-10sim: riscv: move libsim.a creation to top-levelMike Frysinger2-6/+21
The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects.
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker9-9/+9
This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
All the runtimes were only initializing a single CPU. When SMP is enabled, things quickly crash as none of the other CPU structs are setup. Change the default from 0 to the compile time value.
2022-12-23sim: riscv: move arch-specific settings to internal headerMike Frysinger5-55/+83
There's no need for these settings to be in sim-main.h which is shared with common/ sim code, so move it all out to a new header which only this port will include. We can also move the machs.h include out since the model logic was all generalized from compile-time to runtime last year.
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-0/+2
Not all arches include this in sim-main.h, and the ones that do don't actually use bfd defines in the sim-main.h header. Prune it to make sim-main.h simpler so we can kill it off entirely in the future. We add the include to the files that utilize e.g. bfd_vma though.
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
Since SIM_ADDR is always 32-bit, it might truncate the address with 64-bit ELFs. Since we load that addr from the bfd, use the bfd_vma type which matches the bfd_get_start_address API.
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
All ports should be migrated now. Drop the SIM_HAVE_COMMON_SIM_CPU knob and require it be used everywhere now.
2022-12-21sim: riscv: invert sim_cpu storageMike Frysinger3-191/+258
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
These headers define the register numbers for each port to implement the sim_fetch_register & sim_store_register interfaces. While gdb uses these, the APIs are part of the sim, not gdb. Move the headers out of the gdb/ include namespace and into sim/ instead.
2022-11-07sim: riscv: add missing AC_MSG_RESULT callMike Frysinger1-0/+1
Previous commit in here forgot to include this.
2022-11-07sim: riscv: drop subdir configure logicMike Frysinger5-3129/+23
We've been using this only to set the default word size to 32-vs-64 based on the $target. We can easily merge this with the top-level configure script to clean things up a bit.
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+25
Automake will run each subdir individually before moving on to the next one. This means that the linking phase, a single threaded process, will not run in parallel with anything else. When we have to link ~32 ports, that's 32 link steps that don't take advantage of parallel systems. On my really old 4-core system, this cuts a multi-target build from ~60 sec to ~30 sec. We eventually want to move all compile+link steps to this common dir anyways, so might as well move linking now for a nice speedup. We use noinst_PROGRAMS instead of bin_PROGRAMS because we're taking care of the install ourselves rather than letting automake process it.
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
These functions only read from memory, so mark the pointer as const.
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-5/+5
When reading/writing arbitrary data to the system's memory, the unsigned char pointer type doesn't make that much sense. Switch it to void so we align a bit with standard C library read/write functions, and to avoid having to sprinkle casts everywhere.
2022-10-23sim: mips/ppc/riscv: re-add AC_CANONICAL_SYSTEM [PR sim/29439]Mike Frysinger2-0/+162
These configure scripts check $target and change behavior. They shouldn't be doing that, but until we can rework the sim to change behavior based on the input ELF, restore AC_CANONICAL_SYSTEM to these so that $target is correctly populated. This was lost in the d3562f83a7b8a1ae6e333cd5561419d3da18fcb4 ("sim: unify toolchain probing logic") refactor as the logic was hoisted up to the common code. But the fact the vars weren't passed down to the sub-configure scripts was missed. Bug: https://sourceware.org/PR29439
2022-10-11sim/riscv: fix multiply instructions on simulatorTsukasa OI1-0/+1
After this commit: commit 0938b032daa52129b4215d8e0eedb6c9804f5280 Date: Wed Feb 2 10:06:15 2022 +0900 RISC-V: Add 'Zmmul' extension in assembler. some instructions in the RISC-V simulator stopped working as a new instruction class 'INSN_CLASS_ZMMUL' was added, and some existing instructions were moved into this class. The simulator doesn't currently handle this instruction class, and so the instructions will now cause an illegal instruction trap. This commit adds support for INSN_CLASS_ZMMUL, and adds a test that ensures the affected instructions can be executed by the simulator. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Andrew Burgess <aburgess@redhat.com>
2022-09-05sim/riscv: Complete tidying up with SBREAKTsukasa OI1-3/+3
This commit removes SBREAK-related references on the simulator as it's renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1). sim/ChangeLog: * riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
This was left in subdirs because of the dynamic cgen usage. However, we can move this breakpoint call to runtime and let gdb detect whether the symbol exists.
2022-01-06sim: riscv: migrate to standard uintXX_t typesMike Frysinger1-28/+28
Move off the sim-specific unsignedXX types and to the standard uintXX_t types that C11 provides.
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker6-6/+6
This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
2021-11-28sim: riscv: switch to new target-newlib-syscallMike Frysinger2-3/+2
Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and riscv has a custom syscall table for its newlib/libgloss port.
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+5
Pass the existing strings data to the callbacks so that common libgloss syscalls can be implemented (which we'll do shortly).
2021-11-16sim: keep track of program environment stringsMike Frysinger1-0/+6
We've been passing the environment strings to sim_create_inferior, but most ports don't do anything with them. A few will use ad-hoc logic to stuff the stack for user-mode programs, but that's it. Let's formalize this across the board by storing the strings in the normal sim state. This will allow (in future commits) supporting more functionality in the run interface, and to unify some of the libgloss syscalls.
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
We use the program argv to both find the program to run (argv[0]) and to hold the arguments to the program. Most of the time this is fine, but if we want to let programs specify argv[0] independently (which is possible in standard *NIX programs), this double duty doesn't work. So let's split the path to the program to run out into a separate field by itself. This simplifies the various sim_open funcs too. By itself, this code is more of a logical cleanup than something that is super useful. But it will open up customization of argv[0] in a follow up commit. Split the changes to make it easier to review.
2021-10-31sim: drop unused targ-vals.h includesMike Frysinger1-2/+0
This is used in a few places where it's not needed. Drop the include to avoid the build-time generated header file as we move to drop it.
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree.
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger2-2/+4
Move these options up to the common dir so we only test & export them once across all ports. The setting only affects igen based ports, and they were turning this on by default, so keep the default in place.
2021-06-30sim: unify scache settingsMike Frysinger2-2/+4
The cgen scache module is enabled by every cgen port, and with the same default value of 16k (which matches the common default value). Let's pull this option out of the individual ports (via CPPFLAGS) and into the common code (via config.h). The object itself is compiled only for cgen ports atm, so that part doesn't change. The scache code is initialized dynamically via the modules.c logic. That's why the profile code needs an additional CGEN_ARCH check. This will allow us to collapse arch configure files more. Merging the source files will require more future work, but integrating the cgen & non-cgen worlds itself will take a lot.
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-37/+8
This kills off another compile-time option by moving the setting to the individual arch runtimes. This will allow dynamic selection by the arch when doing a single build with multiple arches. The sim_model_init rework is a little funky. In the past it was disabled entirely if no default model was set. We maintain the spirit of the logic by gating the fallback logic on whether the port has defined any models.
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
We want to do a single build with all arches in one binary which means we need to namespace sim_machs on a per-arch basis. Move it from a global variable to the sim description structure so it can be setup at runtime. Changing the SIM_MODEL->num from an enum to an int is unfortunate, but we specifically don't want to maintain a centralized list anymore, and this was never used directly in common code, just passed to per-arch callbacks.
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
The array of pointers is never modified, so mark it const so it ends up in the read-only data section.
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
These ports only use the pieces that have been unified, so we can merge them into the common configure script and get rid of their unique one entirely. We still compile & link separate run programs, and have dedicated subdir Makefiles, but the configure script portion is merged.
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
Move these options up to the common dir so we only test & export them once across all ports.
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-37/+29
The sim-hardware configure option allows builders to select a set of device models to enable. But this seems like unnecessary overkill: the existence of individual device models doesn't affect performance at all as they are only enabled at runtime if the config uses them, and individually these are all <5KB a piece. Stripping off a total of ~50KB from a ~1MB binary doesn't seem useful, and it's extremely unlikely anyone will ever bother. So let's simplify the configure/make logic by turning sim-hardware into a boolean option like many of the other sim options. Any ports that have unique device models will declare them in their Makefile instead of at configure time. This will allow us to (eventually) unify the setting into the common dir.
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
Now that we've moved all content out to the common file, this is empty and can be deleted it entirely.
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
Move these options up to the common dir so we only test & export them once across all ports. This takes a page from the cgen maint logic to make $(MAINT) work for non-automake Makefiles which will allow us to merge it together.
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
This will allow us to build the common code with the same inline settings as the arch subdirs, and only do the test once.
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
Move these options up to the common dir so we only test & export them once across all ports.
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
The common dir is already probing this info since it's using automake, so pass it down to the subdirs so they don't have to probe it at all.
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
Move these options up to the common dir so we only test & export them once across all ports.
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
Move these options up to the common dir so we only test & export them once across all ports.