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| author | Mike Frysinger <vapier@gentoo.org> | 2021-07-06 23:56:13 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-10-31 04:53:22 -0400 |
| commit | f9bfc01578acfde8de7c5c1172732fb2a76caa95 (patch) | |
| tree | b937032c1e3a0dfd58ed59d80c23615bac59888a /sim/riscv | |
| parent | cd3ee89d386d37b5b4db34427f5e1dd9e0f63ad2 (diff) | |
| download | gdb-f9bfc01578acfde8de7c5c1172732fb2a76caa95.zip gdb-f9bfc01578acfde8de7c5c1172732fb2a76caa95.tar.gz gdb-f9bfc01578acfde8de7c5c1172732fb2a76caa95.tar.bz2 | |
sim: drop unused targ-vals.h includes
This is used in a few places where it's not needed. Drop the include
to avoid the build-time generated header file as we move to drop it.
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 0faf939..d2d4cdd 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -34,8 +34,6 @@ #include "opcode/riscv.h" #include "gdb/sim-riscv.h" - -#include "targ-vals.h" #define TRACE_REG(cpu, reg) \ TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \ |