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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-09-04 07:45:06 +0000 |
|---|---|---|
| committer | Andrew Burgess <aburgess@redhat.com> | 2022-09-05 09:42:06 +0100 |
| commit | b9593cb70533f28d276ab8d582dfe622aa4591d5 (patch) | |
| tree | e3222ab019a57858835bc10e4aa07d5fcf3d0573 /sim/riscv | |
| parent | 06c00d5feaf78869b42c28f9b5519c922a6dc765 (diff) | |
| download | gdb-b9593cb70533f28d276ab8d582dfe622aa4591d5.zip gdb-b9593cb70533f28d276ab8d582dfe622aa4591d5.tar.gz gdb-b9593cb70533f28d276ab8d582dfe622aa4591d5.tar.bz2 | |
sim/riscv: Complete tidying up with SBREAK
This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).
sim/ChangeLog:
* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/sim-main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 62f4756..30d2f1e 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FENCE_I: TRACE_INSN (cpu, "fence.i;"); break; - case MATCH_SBREAK: - TRACE_INSN (cpu, "sbreak;"); - /* GDB expects us to step over SBREAK. */ + case MATCH_EBREAK: + TRACE_INSN (cpu, "ebreak;"); + /* GDB expects us to step over EBREAK. */ sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP); break; case MATCH_ECALL: |