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| author | Mike Frysinger <vapier@gentoo.org> | 2021-07-01 01:04:48 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-07-01 20:53:00 -0400 |
| commit | 7eb1f99adaa3515463b6082e4a911d8b334e852f (patch) | |
| tree | 914ebe6a8f134e179355d95dd07814b01e11c020 /sim/riscv | |
| parent | 313c332ff2d5cb2a681149254ca73ba041aa8630 (diff) | |
| download | gdb-7eb1f99adaa3515463b6082e4a911d8b334e852f.zip gdb-7eb1f99adaa3515463b6082e4a911d8b334e852f.tar.gz gdb-7eb1f99adaa3515463b6082e4a911d8b334e852f.tar.bz2 | |
sim: unify reserved instruction bits settings
Move these options up to the common dir so we only test & export
them once across all ports.
The setting only affects igen based ports, and they were turning
this on by default, so keep the default in place.
Diffstat (limited to 'sim/riscv')
| -rw-r--r-- | sim/riscv/ChangeLog | 4 | ||||
| -rwxr-xr-x | sim/riscv/configure | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog index ee7246a..e9aa744 100644 --- a/sim/riscv/ChangeLog +++ b/sim/riscv/ChangeLog @@ -1,3 +1,7 @@ +2021-07-01 Mike Frysinger <vapier@gentoo.org> + + * configure: Regenerate. + 2021-06-30 Mike Frysinger <vapier@gentoo.org> * configure: Regenerate. diff --git a/sim/riscv/configure b/sim/riscv/configure index e366d09..577d4cd 100755 --- a/sim/riscv/configure +++ b/sim/riscv/configure @@ -586,7 +586,6 @@ ac_subst_vars='LTLIBOBJS LIBOBJS SIM_COMMON_BUILD_FALSE SIM_COMMON_BUILD_TRUE -sim_reserved_bits sim_float cgen_breaks target_alias @@ -1760,7 +1759,6 @@ ac_config_commands="$ac_config_commands stamp-h" - SIM_COMMON_BUILD_TRUE='#' SIM_COMMON_BUILD_FALSE= |