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2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina6-94/+197
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina3-3/+35
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina9-556/+759
2018-05-15Fix error messages in the NFP sources when building for 32-bit targets.Francois H. Theron2-45/+44
2018-05-09x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2-3/+7
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra3-2/+7
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson2-9/+54
2018-05-08Correct powerpc spe opcode lookupAlan Modra2-6/+12
2018-05-07Simplify VLE handling in print_insn_powerpc().Peter Bergner2-35/+26
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu7-5115/+5285
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu4-14/+23
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner3-44/+39
2018-05-01Fix unintialized memory in aarch64 opcodes.Tamar Christina2-3/+7
2018-04-30This patch adds support to objdump for disassembly of NFP (Netronome Flow Pro...Francois H. Theron10-207/+3545
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist7-15311/+15097
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist7-15097/+15311
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich3-2028/+570
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich3-31/+39
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich5-5220/+5212
2018-04-26x86: x87-related adjustmentsJan Beulich3-24/+30
2018-04-26x86: drop VexImmExtJan Beulich5-8075/+8078
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich3-126/+6
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina2-2/+6
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist7-5219/+5292
2018-04-16Remove sh5 and sh64 supportAlan Modra12-1595/+16
2018-04-16Remove w65 supportAlan Modra10-682/+12
2018-04-16Remove we32k supportAlan Modra3-2/+5
2018-04-16Remove m88k supportAlan Modra9-775/+11
2018-04-16Remove i370 supportAlan Modra10-1113/+12
2018-04-16Remove h8500 supportAlan Modra10-4199/+12
2018-04-16Remove tahoe supportAlan Modra3-2/+5
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu4-38/+16
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist7-5248/+5402
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra10-1244/+12
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu2-6/+8
2018-04-04Update Spanish translations for ld/ opcodes/ and gold/ sub-directoriesNick Clifton2-381/+1048
2018-03-28x86: drop VecESizeJan Beulich5-7936/+7936
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich4-1981/+1979
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich3-487/+83
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2-24/+20
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton6-571/+646
2018-03-22x86: drop pointless VecESizeJan Beulich3-952/+958
2018-03-22x86: drop remaining redundant DispNJan Beulich2-75/+81
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich4-7/+23
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich3-25/+122
2018-03-22x86: fold a few XOP templatesJan Beulich3-236/+50
2018-03-14RISC-V: Add .insn support.Jim Wilson2-0/+78
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton2-3/+7
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu3-2/+7
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu5-5237/+5098
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