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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-03-08 06:41:34 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-03-08 06:41:34 -0800 |
| commit | d3d50934a9101416c3106497d6ea9ce548760253 (patch) | |
| tree | 1f8b1ad5d7b7052323ac1a0d51ef61e189a736f2 /opcodes | |
| parent | 347a87745eab23d8427349787bde4a938a1e8c3e (diff) | |
| download | gdb-d3d50934a9101416c3106497d6ea9ce548760253.zip gdb-d3d50934a9101416c3106497d6ea9ce548760253.tar.gz gdb-d3d50934a9101416c3106497d6ea9ce548760253.tar.bz2 | |
x86-64: Also optimize "clr reg64"
"clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as
"xor reg32, reg32".
gas/
* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
as "xor reg32, reg32".
* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
* testsuite/gas/i386/x86-64-optimize-1.d: Updated.
opcodes/
* i386-opc.tbl: Add Optimize to clr.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 55f8a14..333dd43 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-03-08 H.J. Lu <hongjiu.lu@intel.com> + * i386-opc.tbl: Add Optimize to clr. + * i386-tbl.h: Regenerated. + +2018-03-08 H.J. Lu <hongjiu.lu@intel.com> + * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index a3080be..8286379 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -205,7 +205,7 @@ xor, 2, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byt xor, 2, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } // clr with 1 operand is really xor with 2 operands. -clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 } +clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } adc, 2, 0x10, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 433f257..06b8b96 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -2115,7 +2115,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0 } }, { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, |