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| author | Tamar Christina <tamar.christina@arm.com> | 2018-04-25 13:37:30 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-04-25 13:38:35 +0100 |
| commit | 10bba94bd44045559cfd048cd34376090dd8107a (patch) | |
| tree | c58a6dab6066e3f8e743dc352aa19fdacf7731ec /opcodes | |
| parent | 1e84581ff0b66168d15270079e8a4d2d12948925 (diff) | |
| download | gdb-10bba94bd44045559cfd048cd34376090dd8107a.zip gdb-10bba94bd44045559cfd048cd34376090dd8107a.tar.gz gdb-10bba94bd44045559cfd048cd34376090dd8107a.tar.bz2 | |
Fix the mask for the sqrdml(a|s)h instructions.
Rn is supposed to have a 5 bit range but instead was given 4 bits
causing these instructions to disassemble as unknown instructions.
opcodes/
* aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
gas/
* testsuite/gas/aarch64/rdma.s: Test for larger register numbers.
* testsuite/gas/aarch64/rdma.d: Update results.
* testsuite/gas/aarch64/rdma-directive.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3ae9be4..c287c1f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2018-04-25 Tamar Christina <tamar.christina@arm.com> + + * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. + 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 26fed8e..36afdd1 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2601,8 +2601,8 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), /* AdvSIMD three same extension. */ - RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), - RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), + RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), + RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ), CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ), /* AdvSIMD shift by immediate. */ |