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2023-10-19opcodes: microblaze: Fix bit masking bugNeal Frager2-6/+9
2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager3-3/+39
2023-10-13RISC-V: Add support for numbered ISA mapping stringsJoseph Faulls1-1/+15
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager3-32/+2
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager3-2/+32
2023-10-05microblaze: Add address extension instructionsNeal frager3-10/+23
2023-10-04opcodes: microblaze: Add hibernate and suspend instructionsNeal frager3-1/+13
2023-10-04aarch64: Refactor system register dataVictor Do Nascimento2-1068/+1080
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento2-1/+11
2023-09-27opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush insnsNeal Frager2-17/+20
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich2-1183/+512
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich2-327/+207
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-1028/+662
2023-09-27Add support for "pcaddi rd, symbol"mengqinggang1-1/+1
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford3-94/+85
2023-09-25Revert "arc: Add new opcode functions for ARCv3 ISA."Claudiu Zissulescu15-3872/+3091
2023-09-25Revert "arc: New ARCv3 ISA instruction table"Claudiu Zissulescu1-11422/+0
2023-09-25arc: New ARCv3 ISA instruction tableClaudiu Zissulescu1-0/+11422
2023-09-25arc: Add new opcode functions for ARCv3 ISA.Claudiu Zissulescu15-3091/+3872
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich4-2671/+2670
2023-09-14x86: Vxy naming correctionJan Beulich1-5/+5
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich4-3865/+7726
2023-09-14x86: support AVX10.1/512Jan Beulich2-0/+13
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich4-311/+320
2023-09-08Set insn_type for branch instructions on aarch64Vladimir Mezentsev1-0/+6
2023-09-08PR30793, kvx_reassemble_bundle index 8 out of boundsAlan Modra1-46/+29
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu2-146/+151
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-2/+2
2023-09-01x86: rename CpuPCLMULJan Beulich4-22/+22
2023-09-01x86: drop Size64 from VMOVQJan Beulich2-2/+2
2023-09-01RISC-V: move various alias entriesJan Beulich1-35/+35
2023-08-30RISC-V: Make XVentanaCondOps RV64 onlyTsukasa OI1-2/+2
2023-08-26Simplify definition of GUILETom Tromey4-4/+8
2023-08-26opcodes i386 and ia64 gen file warningsAlan Modra2-3/+5
2023-08-24kvx: fix kvx_reassemble_bundle index 8 out of boundsPaul Iannetta1-2/+2
2023-08-24kvx: workaround gcc-4.5 bugAlan Modra1-2/+4
2023-08-24kvx: use {u,}int32_t and {u,}int64_tPaul Iannetta2-17/+17
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento3-219/+219
2023-08-22kvx_dis_initAlan Modra1-20/+3
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-4/+0
2023-08-19sim --enable-cgen-maintAlan Modra2-2/+8
2023-08-16kvx: New port.Paul Iannetta10-0/+112808
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-1/+1
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI1-0/+12
2023-08-15RISC-V: remove indirection from register tablesJan Beulich2-12/+12
2023-08-12regen configAlan Modra1-21/+52
2023-08-11x86: pack CPU flags in opcode tableJan Beulich4-31432/+4568
2023-08-11RISC-V: Fix opcode entries of "vmsge{,u}.vx"Tsukasa OI1-4/+4
2023-08-09bpf: use w regs in 32-bit non-fetch atomic pseudo-cDavid Faust1-4/+4
2023-08-07RISC-V: move comment describing rules for riscv_opcodes[]Jan Beulich1-10/+10
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