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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-30 01:04:42 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-30 04:00:40 +0000 |
| commit | fe0f44a0caf59db09ad4bc16a46926aba96ce60d (patch) | |
| tree | 745bdcb298f35b3441dfc52ea3455fb225e15b49 /opcodes | |
| parent | aa1e22eb8d685d456469f3da7933f9215b4d79ef (diff) | |
| download | gdb-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.zip gdb-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.tar.gz gdb-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.tar.bz2 | |
RISC-V: Make XVentanaCondOps RV64 only
Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's manual
only defines them only for RV64 (because all Ventana's processors implement
RV64).
This commit limits XVentanaCondOps instructions RV64-only to match the
behavior of the manual and LLVM.
Note that this commit alone will not make XVentanaCondOps extension with
RV32 invalid (it just makes XVentanaCondOps on RV32 empty).
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and "vt.maskcn"
to XLEN=64.
gas/ChangeLog:
* testsuite/gas/riscv/x-ventana-condops-32.d: New failure test.
* testsuite/gas/riscv/x-ventana-condops-32.l: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 067e9fd..f541660 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2174,8 +2174,8 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ -{"vt.maskc", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, -{"vt.maskcn", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, +{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, +{"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} |