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| author | David Faust <david.faust@oracle.com> | 2023-08-09 11:44:38 -0700 |
|---|---|---|
| committer | David Faust <david.faust@oracle.com> | 2023-08-09 13:51:50 -0700 |
| commit | 6bf6f9245ac56a7ca6eb52a07fc2153b921c5fd6 (patch) | |
| tree | 90e78f615d68170b41b60fa1a21e766a17a7c513 /opcodes | |
| parent | 3cdc2d7e66ab6a48014dcd425c88cfd42a964321 (diff) | |
| download | gdb-6bf6f9245ac56a7ca6eb52a07fc2153b921c5fd6.zip gdb-6bf6f9245ac56a7ca6eb52a07fc2153b921c5fd6.tar.gz gdb-6bf6f9245ac56a7ca6eb52a07fc2153b921c5fd6.tar.bz2 | |
bpf: use w regs in 32-bit non-fetch atomic pseudo-c
The 32-bit non-fetching atomic instructions treat the source register as
32-bits, which means in the pseudo-c syntax the "w" registers should be
used rather than the "r" registers.
opcodes/
* bpf-opc-c (bpf_opcodes): Use %sw for AAD32, AOR32, AAND32
and AXOR32 pseudo-c dialect asm templates.
gas/
* testsuite/gas/bpf/atomic-be-pseudoc.d: Use "w" for source reg
in non-fetching 32-bit atomic instructions.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/bpf-opc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index 3f42680..3d6dccb 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -384,13 +384,13 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR}, /* Atomic instructions (32-bit.) */ - {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) += %sr", + {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) += %sw", BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD}, - {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) |= %sr", + {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) |= %sw", BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR}, - {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) &= %sr", + {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) &= %sw", BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND}, - {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) ^= %sr", + {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "lock%w* ( u32 * ) ( %dr %o16 ) ^= %sw", BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR}, /* Atomic instructions with fetching (32-bit.) */ |