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2023-02-03bpf: fix error conversion from long unsigned int to unsigned int ↵Guillermo E. Martinez2-26/+30
[-Werror=overflow] Regenerating BPF target using the maintainer mode emits: .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow] 57 | 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } The use of a narrow size to handle the mask CGEN in instruction format is causing this error. Additionally eBPF `call' instructions constructed by expressions using symbols (BPF_PSEUDO_CALL) emits annotations in `src' field of the instruction, used to identify BPF target endianness. cpu/ * bpf.cpu (define-call-insn): Remove `src' field from instruction mask. include/ *opcode/cge.h (CGEN_IFMT): Adjust mask bit width. opcodes/ * bpf-opc.c: Regenerate.
2023-02-03RISC-V: don't disassemble unrecognized insns as .byteJan Beulich1-30/+20
Insn width granularity being 16 bits, producing byte granular output isn't very useful. With there being a way to specific otherwise unknown insns to the assembler, use that same representation (to be precise: its <length>,<encoding> flavor) for disassembly.
2023-01-31RISC-V: make C-extension JAL available again for (32-bit) assemblyJan Beulich1-1/+1
Along with the normal JAL alias, the C-extension one should have been moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for consistent alias handling"), for the assembler to actually be able to use it where/when possible. Since neither this nor any other compressed branch insn was being tested so far, take the opportunity and introduce a new testcase covering those.
2023-01-27x86: use ModR/M for FPU insns with operandsJan Beulich3-216/+216
This is the correct way of expressing things; encoding the ModR/M byte directly in base_opcode has always been bogus.
2023-01-27opcodes: suppress internationalization on build helper toolsJan Beulich3-47/+2
While one of the two actually having been instrumented (i386-gen.c) now has that instrumentation dropped, there's still no point in honoring such instrumentation in general (i.e. now for ia64-gen.c only), as that only leads to a waste of resources. With CFILES then being merely an alias of LIBOPCODES_CFILES, drop the former variable altogether.
2023-01-27x86: remove internationalization from i386-gen.cJan Beulich1-26/+23
This is a build time helper utility, which doesn't require translation.
2023-01-20x86: split i386-gen's opcode hash entry structJan Beulich1-23/+28
All glibc malloc() implementations I've checked have a smallest allocation size worth of 3 pointers, with an increment worth of 2 pointers. Hence mnemonics with multiple templates can be stored more efficiently when maintaining the shared "name" field only in the actual hash entry. (To express the shared nature, also convert "name" to by pointer-to-const.) While doing the conversation also pull out common code from the involved if/else construct in expand_templates().
2023-01-20x86: embed register and alike names in disassemblerJan Beulich1-34/+34
Register names are (including their nul terminators) on average almost 4 bytes long. Otoh no register name is longer than 8 bytes. Hence even for 32-bit builds using a pointer is only slightly more space efficient than embedding the strings. A level of indirection can be also avoided by embedding the names as an array of 8 characters directly in the arrays, and the number of base relocations in libopcodes.so (or PIE builds of statically linked executables) goes down as well. To amortize for the otherwise reduced folding of string literals by the linker, use att_names_seg[] in place of string literals in append_seg() and OP_ESreg().
2023-01-20x86: embed register names in reg_entryJan Beulich1-1/+1
Register names are (including their nul terminators) on average almost 4 bytes long. Otoh no register name is longer than 7 bytes. Hence even for 32-bit builds using a pointer is only slightly more space efficient than embedding the strings. A level of indirection can be also avoided by embedding the names as an array of 8 characters directly in the struct, and the number of base relocations in PIE builds of gas goes down as well.
2023-01-20x86: absorb allocation in i386-genJan Beulich1-2/+5
When generating the mnemonic string table we already set up an identifier for the following entry in a number of cases. Re-use that on the next loop iteration rather than re-doing allocation and conversion.
2023-01-20x86: re-use insn mnemonic strings as much as possibleJan Beulich3-4534/+4216
Compact the mnemonic string table such that the tails of longer mnemonics are re-used for shorter ones, going beyond what compilers would typically do, but matching what ELF linkers may do when processing SHF_MERGE|SHF_STRINGS sections. This reduces table size by about 12.5%.
2023-01-20x86: move insn mnemonics to a separate tableJan Beulich6-3835/+8549
Using full pointers to reference the insn mnemonic strings is not very efficient. With overall string size presently just slightly over 20k, even a 16-bit value would suffice. Use "unsigned int" for now, as there's no good use we could presently make of the otherwise saved 16 bits. For 64-bit builds this reduces table size by 6.25% (prior to the recent ISA extension additions it would have been 12.5%), with a similar effect on cache occupation of table entries accessed. For PIE builds of gas this also reduces the number of base relocations quite a bit (obviously independent of bitness).
2023-01-03opcodes: xtensa: fix jump visualization for FLIXMax Filippov1-3/+20
opcodes/ * xtensa-dis.c (print_insn_xtensa): Add local variables insn_type, target and imm_pcrel to track control flow across multiple slots.
2023-01-03opcodes: xtensa: implement styled disassemblyMax Filippov1-11/+22
opcodes/ * xtensa-dis.c (print_xtensa_operand) (print_insn_xtensa): Replace fprintf_func with fprintf_styled_func.
2023-01-03Updated translations for various languages and sub-directoriesNick Clifton4-1544/+1453
2023-01-01Update year range in copyright notice of binutils filesAlan Modra274-278/+278
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-12-31Update version number and regenerate filesNick Clifton2-254/+264
2022-12-31Add markers for 2.40 branchNick Clifton1-0/+4
2022-12-22x86: correct/improve TSX controlsJan Beulich2-1/+32
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx" extension option covering both RTM and HLE, paralleling the "abm" one we already have.
2022-12-22x86: add dependencies on SVMEJan Beulich2-7/+49
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES, and yet in turn RMPQUERY is a SNP extension. Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains unused (just like CPU_SNP_FLAGS already is).
2022-12-22x86: add dependencies on VMXJan Beulich2-2/+33
Both EPT and VMFUNC are extensions to VMX.
2022-12-22x86: correct XSAVE* dependenciesJan Beulich2-8/+10
Like various other features AMX-TILE takes XSAVE as a prereq. XSAVES, unconditionally using compacted format, in turn effectively takes XSAVEC as a prereq (an SDM clarification to this effect is in the works).
2022-12-22x86: correct dependencies of a few AVX512 sub-featuresJan Beulich2-10/+10
Like AVX512-FP16, several other extensions require wider than 16-bit mask registers. As a result they take AVX512BW as a prereq, not (just) AVX512F. Which in turn points out wrong expectations in the noavx512-1 testcase.
2022-12-22x86: add dependencies on AVX2Jan Beulich2-9/+31
Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating on up to 256-bit packed integer vectors.
2022-12-22x86: correct SSE dependenciesJan Beulich2-48/+92
SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI and KL take SSE2 as a prereq, for operating on packed integers. And while correcting KL also record it as a prereq to WIDEKL.
2022-12-22x86: re-work ISA extension dependency handlingJan Beulich2-997/+883
Getting both forward and reverse ISA dependencies right / consistent has been a permanent source of mistakes. Reduce what needs specifying manually to just the direct forward dependencies. Transitive forward dependencies as well as reverse ones are now derived and hence cannot go out of sync anymore (at least in the vast majority of cases; there are a few special cases to still take care of manually). In the course of this several CPU_ANY_*_FLAGS disappear, requiring adjustment to the assembler's cpu_arch[]. Note that to retain the correct reverse dependency of AVX512F wrt AVX512-VP2INTERSECT, the latter has the previously missing AVX512F prereq added. Note further that to avoid adding the following undue prereqs: * ATHLON, K8, and AMDFAM10 gain CMOV and FXSR, * IAMCU gains 387, auxiliary table entries (including a colon-separated modifier) are introduced in addition to the ones representing from converting the old table. To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a) (i.e. "nosse" not disabling AVX), reverse dependency tracking is artifically suppressed. As a side effect disabling of SSE or SSE2 will now also disable AES, PCLMUL, and SHA (respective elements were missing from CPU_ANY_SSE2_FLAGS).
2022-12-21x86: rename CheckRegSize to CheckOperandSizeJan Beulich3-511/+511
While originally indeed used for register size checking only, the attribute has been used for memory operand size checking as well already for quite a while, with more such uses recently having been added.
2022-12-20Re: x86: remove i386-opc.cAlan Modra1-1/+0
Regen opcodes/po/POTFILES.in
2022-12-19x86: omit Cpu prefixes from opcode tableJan Beulich2-2220/+2238
These enumerators can be used in only one specific field, and hence the Cpu prefix isn't needed ther for disambiguation / name space separation.
2022-12-16x86: change representation of extension opcodeJan Beulich3-2286/+2288
Having a "None" field in the vast majority of entries is needlessly cluttering the overall table. Instead of this being a separate field, use a representation matching that of Intel SDM and AMD PM for the main use of the field: Append the value after a / as the separator.
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2-945/+892
PR gas/29524 Having templates with a suffix explicitly present has always been quirky. After prior adjustment all that's left to also eliminate the anomaly from move-with-sign-extend is to consolidate the insn templates and to make may_need_pass2() cope (plus extend testsuite coverage).
2022-12-12x86: drop (now) stray IsStringJan Beulich2-26/+26
The need for them on the operand-less string insns has gone away with the removal of maybe_adjust_templates() and associated logic. Since i386_index_check() needs adjustment then anyway, take the opportunity and also simplify it, possible again as a result of said removal (plus the opcode template adjustments done here).
2022-12-12x86: re-work insn/suffix recognitionJan Beulich2-1290/+1118
Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ↵Jan Beulich1-2/+14
and LSL" This reverts the disassembler parts of 859aa2c86dc9 ("x86: Allow 16-bit register source for LAR and LSL"), adjusting testcases as necessary. That change was itself a partial revert of c9f5b96bdab0 ("x86: correct handling of LAR and LSL"), without actually saying so. While the earlier commit was properly agreed upon, the partial revert was not, and hence should not have been committed. This is even more so that the revert part of that change wasn't even necessary to address PR gas/29844.
2022-12-12x86: generate template sets data at build timeJan Beulich2-1/+2350
Speed up gas startup by avoiding runtime allocation of the instances of type "templates". At the same time cut the memory requirement to just very little over half (not even accounting for any overhead notes_alloc() may incur) by reusing the "end" slot of a preceding entry for the "start" slot of the subsequent one.
2022-12-12x86: drop sentinel from i386_optab[]Jan Beulich2-23/+0
Now that the table is local to gas, ARRAY_SIZE() can be used to determine the end of the table. Re-arrange the processing loop in md_begin() accordingly, at the same time folding the two calls to notes_alloc() into just one.
2022-12-12x86: remove i386-opc.cJan Beulich5-36/+8
Remove the now empty i386-opc.c. To compensate, tie table generation in opcodes/ to the building of i386-dis.o, despite the file not really depending on the generated data.
2022-12-12x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich4-13/+7
Unlike many other architectures, x86 does not share an opcode table between assembly and disassembly. Any consumer of libopcodes would only ever access one of the two. Since gas is the only consumer of the assembly data, move it there. While doing so mark respective entities "static" in i386-gen (we may want to do away with i386_regtab_size altogether). This also shrinks the number of relocations to be processed for libopcodes.so by about 30%.
2022-12-07PowerPC: Add support for RFC02655 - Saturating Subtract InstructionPeter Bergner1-0/+9
opcodes/ * ppc-opc.c (XOL): New define. (XOL_MASK): Likewise. (powerpc_opcodes): Add subfus, subfus., subwus, subwus., subdus, subdus. gas/ * testsuite/gas/ppc/rfc02655.s: New test. * testsuite/gas/ppc/rfc02655.d: Likewise * testsuite/gas/ppc/future-raw.s: Likewise. * testsuite/gas/ppc/future-raw.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run them.
2022-12-07PowerPC: Add support for RFC02656 - Enhanced Load Store with Length InstructionsPeter Bergner1-0/+13
opcodes/ * ppc-opc.c (PPCVSXF): New define. (powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl, stxvrll, stxvprl, stxvprl. gas/ * testsuite/gas/ppc/rfc02656.s: New test. * testsuite/gas/ppc/rfc02656.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it.
2022-12-06x86: Remove unnecessary vex.w check for xh_mode in disassemblerHaochen Jiang1-17/+12
For all the xh_mode usage in table, they are all using %XH, which will print "{bad}" while EVEX.W=1. This makes this vex.w check unnecessary. opcodes/ChangeLog: * i386-dis.c (OP_E_memory): Remove vex.w check for xh_mode.
2022-12-05libopcodes/mips: add support for disassembler stylingAndrew Burgess2-109/+201
This commit adds disassembler styling support for MIPS. After this commit objdump and GDB will style disassembler output. This is a pretty straight forward change, we switch to use the disassemble_info::fprintf_styled_func callback, and pass an appropriate style through as needed. No additional tricks were needed (compared to say i386, or ARM). Tested by running all of the objdump commands used by the gas testsuite and manually inspecting the styled output, everything looks reasonable, though I'm not a MIPS expert, so it is possible that I've missed some corner cases. Worst case though is that something will be styled incorrectly, the actual content should be unchanged. All the gas, ld, and binutils tests still pass for me.
2022-12-05opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess1-3/+6
While working on disassembler styling for MIPS, I noticed that undefined instructions are printed by the disassembler as raw number with no assembler directive prefix (e.g. without .word or .short). I think adding something like .word, or .short, helps to make it clearer the size of the value that is being displayed, and is inline with what many of the other libopcode disassemblers do. In this commit I've added the .word and .short directives, and updated all the tests that I spotted that failed as a result.
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu3-18/+6
Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
2022-12-02x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2-287/+0
With the general use of C99 there's no need anymore to have i386-gen produce these. For more frequently used ones introduce local #define-s, while others are simply spelled out directly. While doing this move some static constants into more narrow scopes. Note that as a "side effect" this corrects type_names[]'es imm8s entry.
2022-12-02x86: also use D for XCHG and TESTJan Beulich2-57/+9
Leverage the C (commutative) attribute to also reduce the number of XCHG and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for XCHG) forms can also be folded into a single template each, utilizing D.
2022-12-01opcodes: Remove i386-init.h and i386-tbl.h from HFILESH.J. Lu3-6/+0
i386-init.h and i386-tbl.h are generated files. There is nothing to translate. Remove them from HFILES (POTFILES). * Makefile.am (HFILES): Remove i386-init.h and i386-tbl.h. * Makefile.in: Regenerated. * po/POTFILES.in: Likewise.
2022-12-01x86: drop No_ldSufJan Beulich4-11598/+11594
With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf anymore.
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-4/+4
With the removal of its use for FPU insns the suffix is now finally properly misnamed. Drop its use altogether, replacing it by a separate boolean instead.
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2-8/+8
As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.)
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