x86: Allow 16-bit register source for LAR and LSL

Since LAR and LSL only access 16 bits of the source operand, regardless
of operand size, allow 16-bit register source for LAR and LSL, and always
disassemble LAR and LSL with 16-bit source operand.

gas/

	PR gas/29844
	* testsuite/gas/i386/i386.s: Add tests for LAR and LSL.
	* testsuite/gas/i386/x86_64.s: Likewise.
	* testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax".
	* testsuite/gas/i386/i386-intel.d: Updated.
	* testsuite/gas/i386/i386.d: Likewise.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intelbad.l: Likewise.
	* testsuite/gas/i386/x86_64-intel.d: Likewise.
	* testsuite/gas/i386/x86_64.d: Likewise.

opcodes/

	PR gas/29844
	* i386-dis.c (MOD_0F02): Removed.
	(MOD_0F03): Likewise.
	(dis386_twobyte): Restore larS and lslS.
	(mod_table): Remove MOD_0F02 and MOD_0F03.
	* i386-opc.tbl: Allow 16-bit register source for LAR and LSL.
	* i386-tbl.h: Regenerated.

3 files changed, 6 insertions, 18 deletions

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index edc2ce9..e43666a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -833,8 +833,6 @@ enum
   MOD_0F01_REG_3,
   MOD_0F01_REG_5,
   MOD_0F01_REG_7,
-  MOD_0F02,
-  MOD_0F03,
   MOD_0F12_PREFIX_0,
   MOD_0F12_PREFIX_2,
   MOD_0F13,
@@ -2117,8 +2115,8 @@ static const struct dis386 dis386_twobyte[] = {
   /* 00 */
   { REG_TABLE (REG_0F00 ) },
   { REG_TABLE (REG_0F01 ) },
-  { MOD_TABLE (MOD_0F02) },
-  { MOD_TABLE (MOD_0F03) },
+  { "larS",		{ Gv, Ew }, 0 },
+  { "lslS",		{ Gv, Ew }, 0 },
   { Bad_Opcode },
   { "syscall",		{ XX }, 0 },
   { "clts",		{ XX }, 0 },
@@ -8200,16 +8198,6 @@ static const struct dis386 mod_table[][2] = {
     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
   },
   {
-    /* MOD_0F02 */
-    { "larS",		{ Gv, Mw }, 0 },
-    { "larS",		{ Gv, Ev }, 0 },
-  },
-  {
-    /* MOD_0F03 */
-    { "lslS",		{ Gv, Mw }, 0 },
-    { "lslS",		{ Gv, Ev }, 0 },
-  },
-  {
     /* MOD_0F12_PREFIX_0 */
     { "movlpX",		{ XM, EXq }, 0 },
     { "movhlps",	{ XM, EXq }, 0 },
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3766f32..8c13f85 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -572,7 +572,7 @@ nop, 0x90, None, 0, NoSuf|RepPrefixOk, {}
 // Protection control.
 arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
 lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
 lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
@@ -580,7 +580,7 @@ lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Un
 lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
 lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
 lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
 
 sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e77addf..8286145 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -5344,7 +5344,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
 	  0, 0, 0, 0, 1, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } } } },
@@ -5452,7 +5452,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
 	  0, 0, 0, 0, 1, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
 	  0, 0, 0, 0, 0, 0 } } } },