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| author | Jan Beulich <jbeulich@suse.com> | 2023-01-31 09:47:22 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-01-31 09:47:22 +0100 |
| commit | a3c2d248683e13aafa7362e3da278080a5bb5954 (patch) | |
| tree | 1fa567e7ea7f7fbabb9d58d224edc05a86f607a8 /opcodes | |
| parent | b3a3d7d90800b7c21ce8d82dbdbf17eeab163c7b (diff) | |
| download | gdb-a3c2d248683e13aafa7362e3da278080a5bb5954.zip gdb-a3c2d248683e13aafa7362e3da278080a5bb5954.tar.gz gdb-a3c2d248683e13aafa7362e3da278080a5bb5954.tar.bz2 | |
RISC-V: make C-extension JAL available again for (32-bit) assembly
Along with the normal JAL alias, the C-extension one should have been
moved as well by 839189bc932e ("RISC-V: re-arrange opcode table for
consistent alias handling"), for the assembler to actually be able to
use it where/when possible.
Since neither this nor any other compressed branch insn was being tested
so far, take the opportunity and introduce a new testcase covering those.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6b65296..f67375f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -340,9 +340,9 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, {"jal", 0, INSN_CLASS_I, "a", MATCH_JAL|(X_RA << OP_SH_RD), MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jal", 0, INSN_CLASS_I, "d,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, -{"jal", 32, INSN_CLASS_C, "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS|INSN_JSR }, {"call", 0, INSN_CLASS_I, "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, |