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3 daysaarch64: Add support for sve2p1 pmov instruction.srinath6-221/+409
This patch adds support for followign SVE2p1 instruction, spec is available here [1]. 1. PMOV (to vector) 2. PMOV (to predicate) Both pmov (to vector) and pmov (to predicate) have destination scalable vector register and source scalable vector register respectively as an operand with no suffix and optional index. To handle this case we have added 8 new operands in this patch. AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */ Since the index of the <Zd> operand is optional, the index part is dropped in disassembly in both the cases of "no index" or "zero index". As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D PMOV <Pn>.D, <Zd>{[<imm>]} Example1: Assembly: pmov z5[0], p6.d Disassembly: pmov z5, p6.d Assembly: pmov z5, p6.d Disassembly: pmov z5, p6.d Example2: Assembly: pmov p4.b, z5[0] Disassembly: pmov p4.b, z5 Assembly: pmov p4.b, z5 Disassembly: pmov p4.b, z5 [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
3 daysaarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni2-158/+170
This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
3 daysaarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni2-160/+184
This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
3 daysaarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni2-151/+175
This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is available here [1] [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
3 daysaarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni2-175/+187
This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
3 daysaarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni2-152/+164
This patch adds support for SVE2p1 "orqv" instruction, spec available here [1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
6 daysaarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)Matthieu Longo1-0/+1
This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
6 daysaarch64: add STEP2 feature and its associated registersMatthieu Longo1-0/+1
AArch64 defines new registers for the feature step2 (Enhanced Software Step Extension). step2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
6 daysaarch64: add SPMU2 feature and its associated registersMatthieu Longo1-0/+1
AArch64 defines new registers for the feature spmu2 (System Performance Monitors Extension version 2). spmu2 is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
6 daysaarch64: add E3DSE feature and its associated registersMatthieu Longo1-0/+2
AArch64 defines new registers for the feature e3dse (Delegated SError exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A feature. This patch also adds relevant tests. Regression tested on aarch64-none-elf, and no regression found.
6 daysRISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich1-102/+102
As of 27b33966b18e ("RISC-V: disallow x0 with certain macro-insns") the .match_func field may be NULL for entries used for assembly only, which is the case for the entire table. With .match and .mask both zero the function would only ever succeed anyway. Save almost a hundred base relocations in the final executable by using NULL instead.
6 daysx86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili2-2/+12
Added new macro %SW to CCMPcc to print ".s" after the mnemonic. Before: ccmpbl {dfv=}.s %edx,%eax After: ccmpbl.s {dfv=} %edx,%eax gas/ChangeLog: * testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %SW for CCMPcc swap operands. * i386-dis.c (struct dis386): Added %SW. (putop): Handle %SW.
7 daysSupport APX CFCMOVCui, Lili6-2237/+3269
The CMOVcc instruction proposed by EVEX has four different forms, corresponding to the four possible combinations of EVEX.ND and EVEX.NF values. In the encoder part, when the CFCMOV template supports EVEX_NF, it means that it requires EVEX.NF to be 1. In the decoder part, CFCMOV_Fixup is used to reverse source and destination operands in the 2-operand case. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov when the insn template supports EVEX_NF. * testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov. * testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add cfcmov instructions. * i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov. (putop): Print 'cf' for cfcmov instructions. * i386-opc.h (EVEX_NF): New. * i386-opc.tbl: Add cfcmov instructions. * i386-mnem.h: Regerated. * i386-tbl.h: Regerated.
13 daysx86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2-31/+34
With both sources being registers, these insns are almost commutative; the only extra adjustment needed is inversion of the encoded condition.
13 daysx86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich2-31/+31
The same properties apply there.
13 daysx86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich2-12/+12
..., for differing only in the resulting EFLAGS, which are left untouched anyway. That's a shorter encoding, available as long as certain constraints on operands are met; see code comments. (SHL-by-1 forms may then be subject to further optimization that was introduced earlier.) Note that kind of as a side effect this also converts multiplication by 1 to shift by 0, which is a plain move or even no-op anyway. That could be further shrunk (as could be presence of shifts/rotates by 0 in the original code as well as a fair set of other {nf}-form insns), yet the expectation (for now) is that people won't write such code in the first place.
13 daysx86/APX: optimize certain {nf}-form insns to LEAJan Beulich2-7/+7
..., as that leaves EFLAGS untouched anyway. That's a shorter encoding, available as long as certain constraints on operand size and registers are met; see code comments. Note that this requires deferring to derive encoding_evex from {nf} presence, as in optimize_encoding() we want to avoid touching the insns when {evex} was also used. Note further that this requires want_disp32() to now also consider the opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still report the original mnemonic (or else things can get confusing). While there, correct adjacent mis-indentation.
13 daysx86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2-15/+15
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS.CF, for the NF variants the immediate can be got rid of in that case by switching to a 1-bit rotate in the opposite direction.
13 daysx86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich2-20/+20
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS, for the NF variants we can safely replace ones using 0x80 by the respectively other insn while negating the immediate, saving 3 immediate bytes (just 1 though for 16-bit operand size). Similarly we can replace ones using 1 / -1 by INC/DEC (eliminating the immediate).
13 daysRISC-V: Add Zabha extension CAS instructions.Jiawei1-0/+8
This patch update the cas instruction in Zabha extension [1], when both Zabha and Zacas extension enabled. [1] https://github.com/riscv/riscv-zabha/tags bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension case. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New instructions. * testsuite/gas/riscv/zabha.d: Ditto. * testsuite/gas/riscv/zabha.s: Ditto. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes. (MASK_AMOCAS_B): Ditto. (MATCH_AMOCAS_H): Ditto. (MASK_AMOCAS_H): Ditto. (DECLARE_INSN): New instructions. * opcode/riscv.h (enum riscv_insn_class): New class case. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-06-26aarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento1-12/+12
Following feedback received shortly after the initial commit of the aarch64 instructions for scaling and converting fp8 instructions, this patch addresses the issues raised in the relevant feedback. This includes the following changes: * Standardize all FP8 qualifier-set names. This has resulted in the renaming of QL_V2FP8B8H to QL_V2_HB_LOWER and, likewise, QL_V28H16B to QL_V2_HB_FULL. * Update `FP8_INSN' aarch64_opcode_table[] entries to reflect the new standardized qualifier-set names mentioned above and, in the case of the "fcvtn" entries, also add a leading 0 to their opcode values so they are given as 8 hexadecimal digits in length to ensure consistency in formatting relative to other entries in the table. * Revise the added test-cases so that when checking operand fields in the disassembled binaries, all bits for these fields get tested to ensure they can be toggled on/off by the relevant operand arguments.
2024-06-25aarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919)Jens Remus1-1/+1
The AArch64 instruction table (aarch64-tbl.h) defines the operand Rt_IN_SYS_ALIASES as register number. During assembly it is correctly encoded as register number (reg.regno) in parse_operands. During disassembly it is first correctly decoded as register number (reg.regno) in aarch64_ext_regno called by aarch64_extract_operand, but then erroneously treated as immediate value (imm.value) in aarch64_print_operand. This resolves the assembler test case "gas/aarch64/brbe-brb-inst" to erroneously fail on s390. On AArch64 - being little-endian - the struct aarch64_opnd_info union fields reg.regno and imm.value share their least-significant bits. On s390 - being big-endian - they do not. opcodes/ PR binutils/31919 * aarch64-opc.c: Treat operand Rt_IN_SYS_ALIASES as register number. Bug: https://sourceware.org/PR31919 Fixes: 72476aca8f58 ("aarch64: add Branch Record Buffer extension instructions") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-06-25aarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni2-33/+33
This patch adds missing contraints to FEAT_B16B16 sve2 instructions bfclamp, bfmla and bfmls and add negative tests for all the bfloat instructions. The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.* to maintain consistency in the testsuite. The bfloat16-1-invalid.* tests are modified so that "selected processor does not support" is generated by the assembler, since +b16b16 is not passed in the command line. The bfloat16-2-invalid.* testcase includes the wrong operands bfloat16 tests.
2024-06-25arch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni1-13/+12
The current implementation for the following SVE2p1 instructions add a constraint in aarch64_opcode_table[] array, so that these instruction might be immediately preceded in program order by a MOVPRFX instruction. As per the spec these instruction does not immediately preceded in program order by a MOVPRFX instruction and to fix this issue, SVE2p1_INSNC macro is replaced with SVE2p1_INSN macro for the entries of these instructions in aarch64_opcode_table[] array. List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv.
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni5-209/+206
This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q as mentioned below, for the issues reported here. https://sourceware.org/pipermail/binutils/2024-February/132408.html 1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as predicated instructions and this issue is fixed in this patch by replacing "SVE2p1_INSNC" with "SVE2p1_INSN" macro. 2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed by replacing "SVE_Zt" with "SVE_ZtxN". 3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in this patch. 4) In ld1q/st1q the index in the second argument is optional and if index is xzr and is skipped in the assembly, the index field is ignored by the disassembler. Fixing above mentioned issues helps with following: 1) ld1q and st1q first register operand accepts enclosed figure braces. 2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping sequence of vector registers. For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector registers are added along with short-form of operands for non-wrapping sequence. I have added test using following logic: ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes) ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1> ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg> ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm> ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value) ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value) ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones) ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding. For all the above form of instructions the hyphenated form is preferred for disassembly if there are more than two registers in the list, and the register numbers are monotonically increasing in increments of one.
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni5-28/+24
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th argument an 4-bit unsigned immediate of extq instruction. The instruction encoding is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately precede in program order by a MOVPRFX instruction. Also removed the unused operand AARCH64_OPND_SVE_Zm_imm4. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni8-61/+13
This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way 2nd operand does the encoding and decoding using the [<imm>] value. dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter) and aarch64_ext_sve_index_imm (extractor) is removed in this patch. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti6-834/+1345
This includes: - FEAT_SME_F8F32 (+sme-f8f32) - FEAT_SME_F8F16 (+sme-f8f16) The FP16 addition/subtraction instructions originally added by FEAT_SME_F16F16 haven't been added to Binutils yet. They are also required to be enabled if FEAT_SME_F8F16 is present, so they are included in this patch.
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti8-366/+877
This includes all the instructions under the following features: - FEAT_FP8FMA (+fp8fma) - FEAT_FP8DOT4 (+fp8dot4) - FEAT_FP8DOT2 (+fp8dot2) - FEAT_SSVE_FP8FMA (+ssve-fp8fma) - FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4) - FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com8-100/+208
Introduces instructions for the SME2 lutv2 extension for AArch64. They are documented in the following document: * ARM DDI0602 For both luti4 instructions, we introduced an operand called SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list for parsing but modified that function so that it can accept operands without qualifiers and rejects instructions that have operands with qualifiers but are not supposed to have operands with qualifiers. For disassembly, we modified print_register_list so that it could accept register lists without qualifiers. For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is similar to SME_Ztx4_STRIDED and we could use existing code for parsing, encoding, and disassembly. For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12. This is a ZT0 register with a bit index encoded in [13:12]. It is similar to SME_ZT0_INDEX. We also introduced an iclass named sme_size_12_b so that we can encode size bits [13:12] correctly when only 'b' is allowed as qualifier.
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich2-16/+16
Such are equivalent to simple moves, which are up to 3 bytes shorter to encode (and perhaps also cheaper to execute).
2024-06-21x86: optimize left-shift-by-1Jan Beulich2-52/+52
These can be replaced by adds when acting on a register operand. While for the scalar forms there's no gain in encoding size, ADD generally has higher throughput than SHL. EFLAGS set by ADD are a superset of those set by SHL (AF in particular is undefined there). For the SIMD cases the transformation also reduced code size, by eliminating the 1-byte immediate from the resulting encoding. Note that this transformation is not applied by gcc13 (according to my observations), so would - as of now - even improve compiler generated code.
2024-06-21x86/APX: fix disassembly of byte register operandsJan Beulich1-0/+1
Like for REX/REX2, EVEX-prefixed insns access the low bytes of all registers; %ah...%bh are inaccessible. Reflect this correctly in output, by leveraging REX machinery we already have to this effect.
2024-06-20Revert "Remove LIBINTL_DEP"Alan Modra3-2/+9
This reverts commit e874cbd3879843a83e4bcc4b54cd7107387b1df6. The patch was wrong. LIBINTL_DEP is needed with an in-tree gettext.
2024-06-20Remove LIBINTL_DEPAlan Modra3-9/+2
The intl directory in the source no longer exists. LIBINTL_DEP is thus always empty. Remove references to it. config/ * gettext-sister.m4: Don't AC_SUBST LIBINTL_DEP. bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.am (*_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am (as_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. gdb/ * Makefile.in (INTL_DEPS): Don't set or reference. * configure: Regenerate. gdbserver/ * Makefile.in (INTL_DEPS): Don't set or reference. gdbsupport/ * Makefile.in: Regenerate. * configure: Regenerate. gold/ * Makefile.am (deps_var): Remove LIBINTL_DEP. (incremental_dump_DEPENDENCIES, dwp_DEPENDENCIES): Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * testsuite/Makefile.am (DEPENDENCIES): Remove LIBINTL_DEP. * testsuite/Makefile.in: Regenerate. gprof/ * Makefile.am (gprof_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. ld/ * Makefile.am (ld_new_DEPENDENCIES): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (BUILD_LIBS): Remove LIBINTL. (BUILD_LIB_DEPS): Remove LIBINTL_DEP. * Makefile.in: Regenerate. * configure: Regenerate.
2024-06-19x86: Remove the secondary encoding for ctest.Cui, Lili2-570/+289
There are two encodings for each opcode F6/F7 in ctest, but the second one is never used, so remove it to reduce the size of opcode_tbl.h. opcodes/ChangeLog: * i386-opc.tbl: Removed the secondary insn template for ctest. * i386-tbl.h: Regenerated.
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu1-0/+3
Add SiFive cease extension, https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This aligns LLVM: * https://llvm.org/docs/RISCVUsage.html * https://github.com/llvm/llvm-project/pull/83896 bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'. (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE. (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE. gas/ChangeLog: * doc/c-riscv.texi: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'. * testsuite/gas/riscv/sifive-insns.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask encoding for 'sf.cease'. * opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida1-0/+26
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 The Zacas extension introduce compare-and-swap instructions to operate on 32-bit, 64-bit and 128-bit (RV64 only) data values. It introduces three new instructions: - amocas.w (32-bit CAS) - amocas.d (64-bit CAS) - amocas.q (128-bit CAS, RV64 only) Like other AMOs in the A extension, Zacas instructions have '.aq', '.rl' and '.aqrl' variations. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. (riscv_supported_std_z_ext): Add 'Zacas' extension. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Handle INSN_CLASS_ZACAS case. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zacas-32.d: New test (RV32). * testsuite/gas/riscv/zacas-fail-32.d: Likewise. * testsuite/gas/riscv/zacas-64.d: New test (RV64). * testsuite/gas/riscv/zacas-fail-64.d: Likewise. * testsuite/gas/riscv/zacas.s: New test source. * testsuite/gas/riscv/zacas-fail.s: Likewise. * testsuite/gas/riscv/zacas-fail-32.l: New file. * testsuite/gas/riscv/zacas-fail-64.l: Likewise. include/ChangeLog: * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): Likewise. (amocas_w, amocas_d, amocas_q): Declare instructions. opcodes/ChangeLog: * riscv-opc.c (match_rs2_rd_even): New function. (amocas_w, amocas_d, amocas_q, amocas_w.aq) (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
2024-06-18x86: Fix typo in i386-dis-evex-mod.hCui, Lili1-2/+2
opcodes/ChangeLog: * i386-dis-evex-mod.h: Used MOD_EVEX_MAP4_F8_P_1/MOD_EVEX_MAP4_F8_P_3 instead of MOD_EVEX_MAP4_F8_P1/MOD_EVEX_MAP4_F8_P3.
2024-06-18Remove %ME and used %NE for movbe.Cui, Lili3-10/+14
%ME is added specifically for movbe. Now with %NE, we can use MOD table + %NE to indicate whether a {evex} prefix is needed. opcodes/ChangeLog: * i386-dis-evex-mod.h: Added movbe. * i386-dis-evex.h: Let movbe go through the mod table. * i386-dis.c (struct dis386): Removed %ME. (putop): Removed case ME.
2024-06-18Support APX CCMP and CTESTCui, Lili7-2233/+4165
CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST in the instruction mnemonic, e.g.: ccmp<cc> { dfv=sf , cf , of } %eax, %ecx also add {evex} cmp/test %eax, %ecx as an alias for ccmpt. For the encoder part, add function check_Scc_OszcOperation to parse '{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode, and adjust base_opcode to its normal meaning in install_template. For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags suffixes. gas/ChangeLog: * config/tc-i386.c (OSZC_CF): New. (OSZC_ZF): Ditto. (OSZC_SF): Ditto. (OSZC_OF): Ditto. (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice. (check_Scc_OszcOperations): Handle SCC OSZC flags. (install_template): Add scc and oszc_flags. (build_apx_evex_prefix): Encode SCC and oszc flags bits. (parse_insn): Handle check_Scc_OszcOperations. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add ccmp and ctest. * i386-dis-evex.h: Ditto. * i386-dis.c (struct instr_info): add scc. (struct dis386): Add new micro 'NE','SC' and'DF'. (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn. (putop): Handle %NE, %SC and %DF. * i386-opc.h (SCC): New. * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2024-06-14aarch64: add SPMU system registers missed in f01ae0392edMatthieu Longo1-0/+79
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas6-2448/+2496
The FEAT_BRBE extension provides two aliases of sys: - brb iall (Invalidates all Branch records in the Branch Record Buffer) - brb inj (Injects the Branch Record held in BRBINFINJ_EL1, BRBSRCINJ_EL1, and BRBTGTINJ_EL1 into the Branch Record Buffer) This patch adds: - the feature option "brbe" that must be added for the aliases to be available - a new operand flag AARCH64_OPND_Rt_IN_SYS_ALIASES that warns in a comment when Rt is set to the non default value 0b11111 (it is constrained unpredictable whether the instruction is undefined or behaves as if the Rt field is set to 0b11111). - a new operand flag AARCH64_OPND_BRBOP that encodes and decodes Op2 values from bit 5 - support for the two brb aliases above See: - https://developer.arm.com/documentation/ddi0602/2024-03/Base-Instructions/BRB--Branch-Record-Buffer--an-alias-of-SYS-?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-INJ--Branch-Record-Injection-into-the-Branch-Record-Buffer?lang=en - https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Instructions/BRB-IALL--Invalidate-the-Branch-Record-Buffer?lang=en
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos1-1/+1
This complements the debug instruction set and uses the same encoding as the VR5400/VR5500 devices.
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos1-30/+30
These instructions are not supported by the target even though they are part of the MIPS II specification.
2024-06-10Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki1-30/+30
This reverts commit a2e71b281a9365872451a157767e03a2e89ddaad.
2024-06-10Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki1-1/+1
This reverts commit c41020942b94ea7c5a58de4fed644826e8f0b509.
2024-06-10MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos1-1/+1
2024-06-10MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos1-30/+30
These instructions are not supported by the target even though they are part of the MIPS II specification.
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich4-4223/+4223
Extremely rarely used attributes are inefficient when represented by a separate attribute. Convert it to an operand constraint, as already suggested during review. The collision with RegKludge is pretty simple to resolve.
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