Age | Commit message (Expand) | Author | Files | Lines |
2023-09-15 | x86: fold CpuLM and Cpu64 | Jan Beulich | 4 | -2671/+2670 |
2023-09-14 | x86: Vxy naming correction | Jan Beulich | 1 | -5/+5 |
2023-09-14 | x86: support AVX10.1 vector size restrictions | Jan Beulich | 4 | -3865/+7726 |
2023-09-14 | x86: support AVX10.1/512 | Jan Beulich | 2 | -0/+13 |
2023-09-14 | x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQ | Jan Beulich | 4 | -311/+320 |
2023-09-08 | Set insn_type for branch instructions on aarch64 | Vladimir Mezentsev | 1 | -0/+6 |
2023-09-08 | PR30793, kvx_reassemble_bundle index 8 out of bounds | Alan Modra | 1 | -46/+29 |
2023-09-07 | RISC-V: Clarify the naming rules of vendor operands. | Nelson Chu | 2 | -146/+151 |
2023-09-05 | RISC-V: fold duplicate code in vector_macro() | Jan Beulich | 1 | -2/+2 |
2023-09-01 | x86: rename CpuPCLMUL | Jan Beulich | 4 | -22/+22 |
2023-09-01 | x86: drop Size64 from VMOVQ | Jan Beulich | 2 | -2/+2 |
2023-09-01 | RISC-V: move various alias entries | Jan Beulich | 1 | -35/+35 |
2023-08-30 | RISC-V: Make XVentanaCondOps RV64 only | Tsukasa OI | 1 | -2/+2 |
2023-08-26 | Simplify definition of GUILE | Tom Tromey | 4 | -4/+8 |
2023-08-26 | opcodes i386 and ia64 gen file warnings | Alan Modra | 2 | -3/+5 |
2023-08-24 | kvx: fix kvx_reassemble_bundle index 8 out of bounds | Paul Iannetta | 1 | -2/+2 |
2023-08-24 | kvx: workaround gcc-4.5 bug | Alan Modra | 1 | -2/+4 |
2023-08-24 | kvx: use {u,}int32_t and {u,}int64_t | Paul Iannetta | 2 | -17/+17 |
2023-08-22 | aarch64: Improve naming conventions for A and R-profile architecture | Victor Do Nascimento | 3 | -219/+219 |
2023-08-22 | kvx_dis_init | Alan Modra | 1 | -20/+3 |
2023-08-21 | bpf: correct neg and neg32 instruction encoding | David Faust | 1 | -4/+0 |
2023-08-19 | sim --enable-cgen-maint | Alan Modra | 2 | -2/+8 |
2023-08-16 | kvx: New port. | Paul Iannetta | 10 | -0/+112808 |
2023-08-15 | RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa' | Tsukasa OI | 1 | -1/+1 |
2023-08-15 | RISC-V: Add support for the 'Zihintntl' extension | Tsukasa OI | 1 | -0/+12 |
2023-08-15 | RISC-V: remove indirection from register tables | Jan Beulich | 2 | -12/+12 |
2023-08-12 | regen config | Alan Modra | 1 | -21/+52 |
2023-08-11 | x86: pack CPU flags in opcode table | Jan Beulich | 4 | -31432/+4568 |
2023-08-11 | RISC-V: Fix opcode entries of "vmsge{,u}.vx" | Tsukasa OI | 1 | -4/+4 |
2023-08-09 | bpf: use w regs in 32-bit non-fetch atomic pseudo-c | David Faust | 1 | -4/+4 |
2023-08-07 | RISC-V: move comment describing rules for riscv_opcodes[] | Jan Beulich | 1 | -10/+10 |
2023-08-03 | cris: sprintf optimisation | Alan Modra | 1 | -19/+10 |
2023-08-03 | cris: sprintf sanitizer null destination pointer | Alan Modra | 1 | -6/+1 |
2023-08-03 | Fix Wlto-type-mismatch in opcodes/ft32-dis.c | Tom de Vries | 1 | -1/+1 |
2023-08-02 | Revert "2.41 Release sources" | Sam James | 26 | -10922/+13254 |
2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 26 | -13254/+10922 |
2023-07-31 | bpf: opcodes: fix regression in BPF disassembler | Jose E. Marchesi | 2 | -1/+7 |
2023-07-30 | bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags | Jose E. Marchesi | 3 | -21/+36 |
2023-07-28 | Fix typo in riscv-dis.c comment | Tsukasa OI | 1 | -1/+1 |
2023-07-27 | Support Intel PBNDKB | Hu, Lin1 | 7 | -6040/+6090 |
2023-07-27 | Support Intel SM4 | Haochen Jiang | 7 | -6751/+6825 |
2023-07-27 | Support Intel SM3 | Haochen Jiang | 7 | -6974/+7105 |
2023-07-27 | Support Intel SHA512 | Haochen Jiang | 7 | -7051/+7206 |
2023-07-27 | Support Intel AVX-VNNI-INT16 | konglin1 | 7 | -5622/+9878 |
2023-07-26 | bpf: fix register NEG[32] instructions | Jose E. Marchesi | 2 | -2/+7 |
2023-07-26 | Regen bpf opcodes POTFILE | Alan Modra | 3 | -7/+2 |
2023-07-25 | bpf: Add atomic compare-and-exchange instructions | David Faust | 1 | -0/+12 |
2023-07-25 | bpf: Update atomic instruction pseudo-C syntax | David Faust | 1 | -16/+16 |
2023-07-24 | Updated translations for bfd, gold and opcodes | Nick Clifton | 1 | -372/+341 |
2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 2 | -0/+13 |