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2023-09-15x86: fold CpuLM and Cpu64Jan Beulich4-2671/+2670
2023-09-14x86: Vxy naming correctionJan Beulich1-5/+5
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich4-3865/+7726
2023-09-14x86: support AVX10.1/512Jan Beulich2-0/+13
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich4-311/+320
2023-09-08Set insn_type for branch instructions on aarch64Vladimir Mezentsev1-0/+6
2023-09-08PR30793, kvx_reassemble_bundle index 8 out of boundsAlan Modra1-46/+29
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu2-146/+151
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-2/+2
2023-09-01x86: rename CpuPCLMULJan Beulich4-22/+22
2023-09-01x86: drop Size64 from VMOVQJan Beulich2-2/+2
2023-09-01RISC-V: move various alias entriesJan Beulich1-35/+35
2023-08-30RISC-V: Make XVentanaCondOps RV64 onlyTsukasa OI1-2/+2
2023-08-26Simplify definition of GUILETom Tromey4-4/+8
2023-08-26opcodes i386 and ia64 gen file warningsAlan Modra2-3/+5
2023-08-24kvx: fix kvx_reassemble_bundle index 8 out of boundsPaul Iannetta1-2/+2
2023-08-24kvx: workaround gcc-4.5 bugAlan Modra1-2/+4
2023-08-24kvx: use {u,}int32_t and {u,}int64_tPaul Iannetta2-17/+17
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento3-219/+219
2023-08-22kvx_dis_initAlan Modra1-20/+3
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-4/+0
2023-08-19sim --enable-cgen-maintAlan Modra2-2/+8
2023-08-16kvx: New port.Paul Iannetta10-0/+112808
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-1/+1
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI1-0/+12
2023-08-15RISC-V: remove indirection from register tablesJan Beulich2-12/+12
2023-08-12regen configAlan Modra1-21/+52
2023-08-11x86: pack CPU flags in opcode tableJan Beulich4-31432/+4568
2023-08-11RISC-V: Fix opcode entries of "vmsge{,u}.vx"Tsukasa OI1-4/+4
2023-08-09bpf: use w regs in 32-bit non-fetch atomic pseudo-cDavid Faust1-4/+4
2023-08-07RISC-V: move comment describing rules for riscv_opcodes[]Jan Beulich1-10/+10
2023-08-03cris: sprintf optimisationAlan Modra1-19/+10
2023-08-03cris: sprintf sanitizer null destination pointerAlan Modra1-6/+1
2023-08-03 Fix Wlto-type-mismatch in opcodes/ft32-dis.cTom de Vries1-1/+1
2023-08-02Revert "2.41 Release sources"Sam James26-10922/+13254
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton26-13254/+10922
2023-07-31bpf: opcodes: fix regression in BPF disassemblerJose E. Marchesi2-1/+7
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-21/+36
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
2023-07-27Support Intel PBNDKBHu, Lin17-6040/+6090
2023-07-27Support Intel SM4Haochen Jiang7-6751/+6825
2023-07-27Support Intel SM3Haochen Jiang7-6974/+7105
2023-07-27Support Intel SHA512Haochen Jiang7-7051/+7206
2023-07-27Support Intel AVX-VNNI-INT16konglin17-5622/+9878
2023-07-26bpf: fix register NEG[32] instructionsJose E. Marchesi2-2/+7
2023-07-26Regen bpf opcodes POTFILEAlan Modra3-7/+2
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust1-0/+12
2023-07-25bpf: Update atomic instruction pseudo-C syntaxDavid Faust1-16/+16
2023-07-24Updated translations for bfd, gold and opcodesNick Clifton1-372/+341
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi2-0/+13