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2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich2-3/+3
{disp16} is invalid to use in 64-bit mode, while {disp32} is invalid to use on pre-386 CPUs. The latter, also affecting other (real) prefixes, further requires that like for insns we fully check the CPU flags; till now only Cpu64/CpuNo64 were taken into consideration.
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-0/+25
This patch adds the permission model enhancement and memory attribute index enhancement features and their corresponding system registers in AArch64 assembler. Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE) Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE) Memory Attribute Index Enhancement (FEAT_AIE) Extension to Translation Control Registers (FEAT_TCR2) These features are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-0/+9
This patch adds 3 new AT system instructions through FEAT_ATS1A feature, which are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-0/+14
This patch also adds support for: 1. FEAT_RASv2 feature and "ERXGSR_EL1" system register. RASv2 feature is enabled by passing +rasv2 to -march (eg: -march=armv8-a+rasv2). 2. FEAT_SCTLR2 and following system registers. SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3. 3. FEAT_FGT2 and following system registers. HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 4. FEAT_PFAR and following system registers. PFAR_EL1, PFAR_EL2 and PFAR_EL12. FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default enabled from Armv9.4-A architecture. This patch also adds support for two read only system registers id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from Armv8-A Architecture.
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-0/+1
This patch adds features to the Statistical Profiling Extension, identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which are enabled by default from Armv9.4-A. Also adds support for system register "pmsdsfr_el1".
2023-11-16aarch64: Add SLC target for PRFM instruction.Srinath Parvathaneni1-6/+6
This patch adds support for FEAT_PRFMSLC feature which enables SLC target for PRFM instructions.
2023-11-15Finalized intl-update patchesArsen Arsenovi?7-334/+2410
* intl: Remove directory. Replaced with out-of-tree GNU gettext. * .gitignore: Add '/gettext*'. * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag. Skips appending current flag to bbaseargs. <library exemptions>: Exempt --with-libintl-{type,prefix} from target and build machine argument passing. * configure: Regenerate. * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext. * Makefile.in: Regenerate. * src-release.sh: Remove references to the intl/ directory.
2023-11-10Add support for ilp32 register alias.Lulu Cai2-6/+6
2023-11-09aarch64: Fix error in THE system register checkingVictor Do Nascimento2-4/+1
The erroneous omission of a "reg_value == " in the THE system register encoding check added in [1] led to an error which was not picked up in GCC but which was flagged in Clang due to its use of [-Werror,-Wconstant-logical-operand] check. Together with this fix we add a new test for the THE registers to pick up their illegal use, adding an extra and important layer of validation. Furthermore, in separating system register from instruction implementation (with which only the former was of concern in the cited patch), additions made to `aarch64-tbl.h' are rolled back so that these can be added later when adding THE instructions to the codebase, a more natural place for these changes. [1] https://sourceware.org/pipermail/binutils/2023-November/130314.html opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Fix typo. * aarch64-tbl.h (THE): Remove. (aarch64_feature_set aarch64_feature_the): Likewise. gas/ChangeLog: * testsuite/gas/aarch64/illegal-sysreg-8.l: Add tests for THE system registers. * testsuite/gas/aarch64/illegal-sysreg-8.s: Likewise.
2023-11-09x86: rework UWRMSR operand swappingJan Beulich2-3/+5
As indicated during review already, doing the swapping early is overall cheaper than doing it only after operand matching.
2023-11-09x86: do away with is_evex_encoding()Jan Beulich2-575/+585
As we have grown more uses of it, it becomes increasingly more desirable to replace it by a simpler check. Have i386-gen do at build time what so far was done at runtime: Deal with templates indicating EVEX-encoding by other than the EVex attribute, and set that to "dynamic" in such cases. This then allows simplifying a number of other conditionals as well.
2023-11-09x86: split insn templates' CPU fieldJan Beulich4-474/+4249
Right now the opcode table has entries with ISA restrictions of the form FEAT1|FEAT2, the meaning of which depends on context and requires special treatment in tc-i386.c: Sometimes this means "both features requires", whereas originally it was intended to solely mean "all of these features required". Split the field, with the original one regaining its original meaning. The new field now truly means "any of these". The combination of both fields is still and &&-type check, i.e. (all of these) && (any of these). In the opcode table more involved combinations of features then also need expressing this way: "all" entities first, follow by "any" entities enclosed in parentheses, e.g. x64&(AVX|AVX512F). If the "all" part is empty, parentheses may not be added around the "any" part (unless parsing logic was further relaxed). Note that this way AVX512VL no longer needs as much special treatment, and hence templates previously using AVX512F|AVX512VL are switched to just AVX512VL. Note further that this requires FMA handling as resulting from da0784f961d8 ("x86: fold FMA VEX and EVEX templates") to be slightly re-done: FMA now becomes more similar to AVX and AVX2.
2023-11-09x86: Cpu64 handling improvementsJan Beulich3-52/+90
First of all we want to also accumulate its reverse dependencies, such that we can use them in cpu_flags_match(). This is in particular in preparation of APX additions, such that e.g. BMI VEX-encoding templates can become combined VEX/EVEX ones. Once we have the reverse dependencies, we can further leverage them to omit explicit "&x64" from any insn templates dealing with 64-bit-mode- only ISA extensions. Besides helping readability for several insn templates we already have, this will also help with what is going to be added for APX (as all of the new templates would otherwise need to have "&x64"). Note that rather than leaving a meaningless CPU_64_FLAGS (which is unused anyway), its emitting is now also suppressed.
2023-11-09x86: Intel Core processors do not support CMPXCHG16BJan Beulich2-2/+2
This being a 64-bit-only instruction (see also i386-opc.tbl) it cannot possibly be supported by CPUs not supporting 64-bit mode.
2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento4-2407/+2558
Implement, together with the necessary tests, the following new LSE128 atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); gas/ChangeLog: * testsuite/gas/aarch64/lse128-atomic.d: New. * testsuite/gas/aarch64/lse128-atomic.s: Likewise. opcodes/ChangeLog: * aarch64-tbl.h (ldclrp): new _LSE128_INSN entry. (ldclrpa): Likewise. (ldclrpal): Likewise. (ldclrpl): Likewise. (ldsetp): Likewise. (ldsetpa): Likewise. (ldsetpal): Likewise. (ldsetpl): Likewise. (swpp): Likewise. (swppa): Likewise. (swppal): Likewise. (swppl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+5
Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise.
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento3-0/+8
Given the particular encoding of the LSE128 instructions, create the necessary shared input+output operand register description and handling in the code to allow for the encoding of the LSE128 128-bit atomic operations. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): opcodes/ChangeLog: * aarch64-opc.c (fields): (aarch64_print_operand): * aarch64-opc.h (enum aarch64_field_kind): * aarch64-tbl.h (AARCH64_OPERANDS):
2023-11-07aarch64: Add 128-bit system register flagsVictor Do Nascimento2-10/+13
In preparation for the implementation of 128-bit system register support across the toolchain, this patch adds the feature flag F_REG_128 and adds it to relevant system registers in `aarch64-sys-regs.def'. Given the shared nature of this file, this change is made necessary initially to implement argument validation in the `__arm_rsr128' and `__armwsr128' ACLE intrinsics in GCC, but will be of subsequent use in the binutils implementation of the corresponding `mrrs' and `msrr' instructions. Regression tested on aarch64-linux-gnu, no regressions. opcodes/ChangeLog: * aarch64-opc.h (F_REG_128): New flag. * aarch64-sys-regs.def (par_el1): Add F_REG_128 flag. (rcwmask_el1): Likewise. (rcwsmask_el1): Likewise. (ttbr0_el1): Likewise. (ttbr0_el12): Likewise. (ttbr0_el2): Likewise. (ttbr1_el1): Likewise. (ttbr1_el12): Likewise. (ttbr1_el2): Likewise. (vttbr_el2): Likewise.
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento3-0/+10
Add Binutils support for system registers associated with the Translation Hardening Extension (THE). In doing so, we also add core feature support for THE, enabling its associated feature flag and implementing the necessary feature-checking machinery. Regression tested on aarch64-linux-gnu, no regressions. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier. * doc/c-aarch64.texi (AArch64 Extensions): Update documentation for `the' option. * testsuite/gas/aarch64/sysreg-8.s: Add tests for `the' associated system registers. * testsuite/gas/aarch64/sysreg-8.d: Likewise. include/ChangeLog: * opcode/aarch64.h (enum aarch64_feature_bit): Add AARCH64_FEATURE_THE. opcode/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the' system register check support. * aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1' * aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2-0/+39
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2-0/+37
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+19
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and FS{H,W,D,Q} the sole difference between the handling is the insn mnemonic passed to the common handling functions. The intended mnemonic, however, can easily be retrieved. Furthermore leverags that Sx and FSx are then handled identically, too, and hence their cases can also be folded.
2023-11-02aarch64: Add GCS system registers.Srinath Parvathaneni1-0/+10
This patch adds support for 10 new AArch64 system registers (gcscre0_el1, gcscr_el1, gcscr_el12, gcscr_el2, gcscr_el3, gcspr_el0, gcspr_el1 ,gcspr_el12, gcspr_el2 and gcspr_el3), which are enabled on using Guarded Control Stack (+gcs flag) feature.
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni5-2235/+2248
This patch adds support for Guarded control stack data synchronization instruction (GCSB DSYNC). This instruction is allocated to existing HINT space and uses the HINT number 19 and to match this an entry is added to the aarch64_hint_options array.
2023-11-02aarch64: Add support for GCS extension.srinath4-2510/+2559
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is optional from Armv9.4-A architecture and enabled by passing +gcs option to -march (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file. Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx, gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni2-0/+11
This patch adds support for Check Feature Status Extension (CHK) which is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction (hint #40).
2023-10-31Support Intel USER_MSRHu, Lin17-1166/+1314
This patches aims to support Intel USER_MSR. In addition to the usual support, this patch includes encoding and decoding support for MAP7 and immediate numbers as the last operand (ATT style). gas/ChangeLog: * NEWS: Support Intel USER_MSR. * config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit mode. (build_vex_prefix): Add VEXMAP7. (md_assemble): Handling the imm32 of USER_MSR. (match_template): Handling the unusual immediate. * doc/c-i386.texi: Document .user_msr. * testsuite/gas/i386/i386.exp: Run USER_MSR tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/user_msr-inval.l: New test. * testsuite/gas/i386/user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto. * testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto. * testsuite/gas/i386/x86-64-user_msr.d: Ditto. * testsuite/gas/i386/x86-64-user_msr.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add a new attribute has_skipped_modrm. (Gq): New. (Rq): Ditto. (q_mm_mode): Ditto. (Nq): Change mode from q_mode to q_mm_mode. (VEX_LEN_TABLE): (get_valid_dis386): Add VEX_MAP7 in VEX prefix. and handle the map7_f8 for save space. (OP_Skip_MODRM): Set has_skipped_modrm. (OP_E): Skip codep++ when has skipped modrm byte. (OP_R): Support q_mode and q_mm_mode. (REG_VEX_MAP7_F8_L_0_W_0): New. (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto. (X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto. (VEX_LEN_MAP7_F8): Ditto. (VEX_W_MAP7_F8_L_0): Ditto. (MOD_0F38F8): Ditto. (PREFIX_0F38F8_M_0): Ditto. (PREFIX_0F38F8_M_1_X86_64): Ditto. (X86_64_0F38F8_M_1): Ditto. (PREFIX_0F38F8): Remove. (prefix_table): Add PREFIX_0F38F8_M_1_X86_64. Remove PREFIX_0F38F8. (reg_table): Add REG_VEX_MAP7_F8_L_0_W_0, PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64. (x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1, X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1. (vex_table): Add VEX_MAP7. (vex_len_table): Add VEX_LEN_MAP7_F8, VEX_W_MAP7_F8_L_0. (mod_table): New entry for USER_MSR and add MOD_0F38F8. * i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (SPACE_VEXMAP7): New. (CPU_USER_MSR_FLAGS): Ditoo. (CPU_ANY_USER_MSR_FLAGS): Ditto. (i386_cpu_flags): Add cpuuser_msr. * i386-opc.tbl: Add USER_MSR instructions. * i386-tbl.h: Regenerated.
2023-10-30aarch64: Update aarch64-sys-regs.def headerVictor Do Nascimento1-0/+4
Given the shared use of the aarch64-sys-regs.def file across Binutils and GCC, add instructions for keeping the file synchronized across the two codebases. Namely, it should be made clear that all changes are first to be made in Binutils and the updated file copied across to GCC. opcodes/ChangeLog * opcodes/aarch64-sys-regs.def: Update file-description header comment.
2023-10-28opcodes: bpf-dis.c: fix typo in commentJose E. Marchesi1-1/+1
2023-10-19opcodes: microblaze: Fix bit masking bugNeal Frager2-6/+9
There is currently a bug in the bit masking for the barrel shift instructions because the bit mask is not including all of the register bits which must be zero. With this patch, the disassembler can be sure that the 32-bit value is indeed a barrel shift instruction and not a data value in memory. This fix can be verified by assembling and disassembling the following: .text .long 0x65005f5f With this patch, the bug is fixed, and the objdump will know that 0x65005f5f is not a barrel shift instruction. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-15opcodes: microblaze: Add new bit-field instructionsNeal Frager3-3/+39
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref With version 6 of the patch, no new relocation types are added as this was unnecessary for adding the bsefi and bsifi instructions. FIXED: Segfault caused by incorrect termination of microblaze_opcodes. Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-13RISC-V: Add support for numbered ISA mapping stringsJoseph Faulls1-1/+15
The elf psabi allows for mapping symbols to be of the form $x<ISA>.<any> opcodes/ * riscv-dis.c (riscv_get_map_state): allow mapping symbol to be suffixed by a unique identifier .<any>
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager3-32/+2
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager3-2/+32
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-05microblaze: Add address extension instructionsNeal frager3-10/+23
* microblaze-opcm.h (struct op_code_struct): Tidy and remove redundant entries. * microblaze-opc.h (MAX_OPCODES): Increase to 300. (op_code_struct): Add address extension instructions.
2023-10-04opcodes: microblaze: Add hibernate and suspend instructionsNeal frager3-1/+13
2023-10-04aarch64: Refactor system register dataVictor Do Nascimento2-1068/+1080
This patch moves instances of system register definitions, represented by the SYSREG macro, out of their original place in `aarch64-opc.c' and into a dedicated .def file, `aarch64-sys-regs.def'. System register entries in this new file are ordered alphabetically by name. This choice is made to enable the use of fast search algorithms such as binary search when validating register names. The SYSREG macro, defined as SYSREG (name, encoding, flags, features) is kept as is and used in the def file, but all other SR_* macros which previously served as indirections to SYSREG are removed. opcodes/ChangeLog: * aarch64-opc.c (SR_CORE): Macro definition and uses deleted. (SR_FEAT): Likewise. (SR_FEAT2): Likewise. (SR_V8_1_A): Likewise. (SR_V8_4_A): Likewise. (SR_V8A): Likewise. (SR_V8R): Likewise. (SR_V8_1A): Likewise. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (SR_GIC): Likewise. (SR_AMU): Likewise. (SR_LOR): Likewise. (SR_PAN): Likewise. (SR_RAS): Likewise. (SR_RNG): Likewise. (SR_SME): Likewise. (SR_SSBS): Likewise. (SR_SVE): Likewise. (SR_ID_PFR2): Likewise. (SR_PROFILE): Likewise. (SR_MEMTAG): Likewise. (SR_SCXTNUM): Likewise. (SR_EXPAND_ELx): Likewise. (SR_EXPAND_EL12): Likewise. * opcodes/aarch64-sys-regs.def: New.
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento2-1/+11
This patch adds a mechanism for system register name alias detection to register-matching mechanisms. A new `F_REG_ALIAS' flag is added to the set of register flags and used to label which entries in aarch64_sys_regs[] correspond to aliases (and thus which CPENC values are non-unique in this array). Where this is used is, for example, in `aarch64_print_operand' where, in the case of system register decoding, the aarch64_sys_regs[] array is iterated through until a match in CPENC value is made and the first match accepted. If insufficient care is given in the ordering of system registers in this array, the alias is encountered before the "real" register and used incorrectly as the register name in the disassembled output. With this flag and the new `aarch64_sys_reg_alias_p' test, search candidates corresponding to aliases can be conveniently skipped over. One concrete example of where this is useful is with the `trcextinselr0' system register. It was initially placed in the system register list before `trcextinselr', in contrast to a more natural alphabetical order. include/ChangeLog: * opcode/aarch64.h: add `aarch64_sys_reg_alias_p' prototype. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_reg_alias_p): New. (aarch64_print_operand): add aarch64_sys_reg_alias_p check. (aarch64_sys_regs): Add F_REG_ALIAS flag to "trcextinselr" entry. * aarch64-opc.h (F_REG_ALIAS): New.
2023-09-27opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush insnsNeal Frager2-17/+20
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich2-1183/+512
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for FMA ones as well, requiring one further adjustment to cpu_flags_match().
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich2-327/+207
Following the folding of some generic AVX/AVX2 templates with their AVX512F counterpart ones, do this for VAES and VPCLMULQDQ ones as well.
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich2-1028/+662
In anticipation of APX introduce logic to reduce the number of templates we have now, allowing to limit some the number of ones we then need to gain. The fundamental requirements are that - attributes be compatible, which specifically means VexW needs to be the same in the templates (which often isn't the case, for VEX encodings having far more WIG tha, EVEX ones), - the EVEX form being AVX512F (with or without AVX512VL), not any of its extensions (the same will then be required for APX - it'll need to be APX_F). Note that in check_register() there's now a redundant zmm check. Since this logic will need revisiting for APX anyway, I'd like to keep it that way for now. (Similarly a couple of if()-s which could be folded are kept separate, to reduce code churn when adding APX support.)
2023-09-27Add support for "pcaddi rd, symbol"mengqinggang1-1/+1
Add a macro pcaddi instruction to support "pcaddi rd, symbol". pcaddi has a 20-bit signed immediate, it can address a +/- 2MB pc relative address, and the address should be 4-byte aligned.
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford3-94/+85
The AArch64 feature-flag code is currently limited to a maximum of 64 features. This patch reworks it so that the limit can be increased more easily. The basic idea is: (1) Turn the ARM_FEATURE_FOO macros into an enum, with the enum counting bit positions. (2) Make the feature-list macros take an array index argument (currently always 0). The macros then return the aarch64_feature_set contents for that array index. An N-element array would then be initialised as: { MACRO (0), ..., MACRO (N - 1) } (3) Provide convenience macros for initialising an aarch64_feature_set for: - a single feature - a list of individual features - an architecture version - an architecture version + a list of additional features (2) and (3) use the preprocessor to generate static initialisers. The main restriction was that uses of the same preprocessor macro cannot be nested. So if a macro wants to do something for N individual arguments, it needs to use a chain of N macros to do it. There then needs to be a way of deriving N, as a preprocessor token suitable for pasting. The easiest way of doing that was to precede each list of features by the number of features in the list. So an aarch64_feature_set initialiser for three features A, B and C would be written: AARCH64_FEATURES (3, A, B, C) This scheme makes it difficult to keep AARCH64_FEATURE_CRYPTO as a synonym for SHA2+AES, so the patch expands the former to the latter.
2023-09-25Revert "arc: Add new opcode functions for ARCv3 ISA."Claudiu Zissulescu15-3872/+3091
This reverts commit c99dc76089a2de97ea0ee755aa8e87037a17b6d6.
2023-09-25Revert "arc: New ARCv3 ISA instruction table"Claudiu Zissulescu1-11422/+0
This reverts commit 67036dfacf87e79317984f51892bfc0eda0e597f.
2023-09-25arc: New ARCv3 ISA instruction tableClaudiu Zissulescu1-0/+11422
opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * opcodes/arc64-tbl.h: New file. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-09-25arc: Add new opcode functions for ARCv3 ISA.Claudiu Zissulescu15-3091/+3872
opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cmiranda@synopsys.com> * opcodes/Makefile.am: Add ARC64 opcode file. * opcodes/Makefile.in: Regenerate. * opcodes/arc-opc.c: Move the common functionality to arcxx-opc.inc. Keep only ARCv2 ARCv1 specifics. * opcodes/arc-ext-tbl.h: Deleted file. * opcodes/arcxx-opc.inc: New file. * opcodes/arc64-opc.c: Likewise. * opcodes/arc-fxi.h (insert_uimm9_a32_11_s): New function. (extract_uimm9_a32_11_s): Likewise. (insert_uimm10_13_s): Likewise. (extract_uimm10_13_s): Likewise. * opcodes/configure: Regenerate. * opcodes/configure.ac: Add ARC64 target. * opcodes/disassemble.c: Likewise. * opcodes/arc-dis.c (regmod_t): New type. (regmods): New structure. (fpnames): New strings with fp-regs name. (REG_PCL, REG_LIMM, REG_LIMM_S, REG_U32, REG_S32): New defines. (getregname): New function. (find_format_from_table): Discriminate between signed and unsigned 32bit immediates. (find_format): Handle extract function for flags. (arc_insn_length): Update insn lengths to various architectures. (print_insn_arc): Update printing for various ARC architectures. * opcodes/arc-flag-classes.def: New file. * opcodes/arc-flag.def: New file. * opcodes/arc-operands.def: New file. * opcodes/arc-regs.h: Changed. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich4-2671/+2670
Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while Cpu64 is solely used in insn templates, they no longer need to be treated different from other "ordinary" flags; the only "unusual" one left if CpuNo64. Fold both, leaving just Cpu64.
2023-09-14x86: Vxy naming correctionJan Beulich1-5/+5
Looking at the VEX and EVEX forms of vcvtneps2bf16 I noticed that operand purpose isn't properly reflected in Vxy's definition. Rename "dst" to "src", thus bringing things in line with Exy.
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