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path: root/opcodes/riscv-dis.c
AgeCommit message (Expand)AuthorFilesLines
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-0/+2
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI1-6/+14
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI1-1/+7
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI1-1/+1
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb1-16/+12
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess1-72/+121
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+4
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-1/+1
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu1-1/+3
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess1-9/+138
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-0/+4
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu1-0/+67
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei1-0/+8
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-6/+26
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess1-1/+23
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman1-10/+14
2021-03-31Use bool in opcodesAlan Modra1-7/+7
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-20/+17
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-8/+13
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-1/+1
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-15/+13
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu1-3/+34
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-3/+6
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-0/+1
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-10/+70
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-06-26RISC-V: Make objdump disassembly work right for binary files.Jim Wilson1-1/+5
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-18Include bfd_stdint.h in bfd.hAlan Modra1-1/+1
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+17
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-1/+1
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-1/+1
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-03-03opcodes error messagesAlan Modra1-2/+2
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-1/+1
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson1-0/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-1/+1
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
2017-05-04RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng1-0/+1