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| author | Jim Wilson <jimw@sifive.com> | 2019-06-26 17:17:09 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-06-26 17:17:09 -0700 |
| commit | d7560e2df501c7da1b0e4e64116dd52fe5715a96 (patch) | |
| tree | ffcd2ca790a3e0937d93ba4dbd9101dc46a5f247 /opcodes/riscv-dis.c | |
| parent | 696d5b3801a0e9d6514a92734bde09985f968a2f (diff) | |
| download | gdb-d7560e2df501c7da1b0e4e64116dd52fe5715a96.zip gdb-d7560e2df501c7da1b0e4e64116dd52fe5715a96.tar.gz gdb-d7560e2df501c7da1b0e4e64116dd52fe5715a96.tar.bz2 | |
RISC-V: Make objdump disassembly work right for binary files.
Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian. But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that. This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.
opcodes/
PR binutils/24739
* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
Set info->display_endian to info->endian_code.
Diffstat (limited to 'opcodes/riscv-dis.c')
| -rw-r--r-- | opcodes/riscv-dis.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 764c4d4..40893c3 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -395,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) insnlen = riscv_insn_length (word); + /* RISC-V instructions are always little-endian. */ + info->endian_code = BFD_ENDIAN_LITTLE; + info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; info->bytes_per_line = 8; - info->display_endian = info->endian; + /* We don't support constant pools, so this must be code. */ + info->display_endian = info->endian_code; info->insn_info_valid = 1; info->branch_delay_insns = 0; info->data_size = 0; |