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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-11-30 18:05:13 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-11-30 19:03:48 +0800 |
| commit | abfdb09f011ac7c76321843d9d0b395ca96e3fef (patch) | |
| tree | 1e4a9ea03e6c4084873370a7d83ca7fd4135ce9b /opcodes/riscv-dis.c | |
| parent | ee083a9e7cca3f2946a259303b4594d6329602fd (diff) | |
| download | gdb-abfdb09f011ac7c76321843d9d0b395ca96e3fef.zip gdb-abfdb09f011ac7c76321843d9d0b395ca96e3fef.tar.gz gdb-abfdb09f011ac7c76321843d9d0b395ca96e3fef.tar.bz2 | |
RISC-V: The vtype immediate with more than the defined 8 bits are preserved.
According the rvv spec,
https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc
The bits of vtype immediate from 8 to (xlen - 1) should be reserved.
Therefore, we should also dump the vtype immediate as numbers, when
they are set over 8-bits. I think this is a bug that we used to support
vediv extension and use the bit 8 and 9 of vtype, but forgot to update
the behavior when removing the vediv.
Consider the testcases,
vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used.
vsetvli a0, a1, 0x400 # the reserved bit 10 is used.
vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used.
vsetvli a0, a1, 0x100 # the reserved bit 8 is used.
vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used.
vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used.
The original objdump shows the following result,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu
c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu
10: f005f557 vsetivli a0,11,e8,m1,tu,mu
14: d005f557 vsetivli a0,11,e8,m1,tu,mu
But in fact the correct result should be,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,768
c: 1005f557 vsetvli a0,a1,256
10: f005f557 vsetivli a0,11,768
14: d005f557 vsetivli a0,11,256
gas/
* testsuite/gas/riscv/vector-insns.d: Added testcases to
test the reserved bit 8 to (xlen-1) of vtype.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES,
since they are different for operand Vc and Vb.
opcodes/
* riscv-dis.c (print_insn_args): Updated imm_vtype_res to
extract the reserved immediate of vtype correctly.
Diffstat (limited to 'opcodes/riscv-dis.c')
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index a3c8506..d646dd5 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -328,7 +328,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm); unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm); unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm); - unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm); + unsigned int imm_vtype_res = (imm >> 8); if (imm_vsew < ARRAY_SIZE (riscv_vsew) && imm_vlmul < ARRAY_SIZE (riscv_vlmul) |