aboutsummaryrefslogtreecommitdiff
path: root/opcodes/riscv-dis.c
AgeCommit message (Expand)AuthorFilesLines
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+4
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+16
2023-05-19RISC-V: Minor improvements for dis-assembler.Nelson Chu1-21/+37
2023-04-18RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng1-0/+43
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-5/+21
2023-03-21RISC-V: Fix disassemble fetch fail return value.Jiawei1-2/+2
2023-02-03RISC-V: don't disassemble unrecognized insns as .byteJan Beulich1-30/+20
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-28RISC-V: Better support for long instructions (disassembler)Tsukasa OI1-5/+9
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+9
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-0/+2
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI1-6/+14
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI1-1/+7
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI1-1/+1
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb1-16/+12
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess1-72/+121
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+4
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-1/+1
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu1-1/+3
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess1-9/+138
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-0/+4
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu1-0/+67
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei1-0/+8
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-6/+26
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess1-1/+23
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman1-10/+14
2021-03-31Use bool in opcodesAlan Modra1-7/+7
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1