RISC-V: Add support for the Zfa extension

This patch adds support for the RISC-V Zfa extension,
which introduces additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of FP registers in case XLEN < FLEN
* fleq/fltq (quiet comparison instructions)

Zfa defines its instructions in combination with the following
extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)

This patch is based on an earlier version from Tsukasa OI:
  https://sourceware.org/pipermail/binutils/2022-September/122939.html
Most significant change to that commit is the switch from the rs1-field
value to the actual floating-point value in the last operand of the fli*
instructions. Everything that strtof() can parse is accepted and
the '%a' printf specifier is used to output hex floating-point literals
in the disassembly.

The Zfa specification is frozen (and has passed public review).  It is
available as a chapter in "The RISC-V Instruction Set Manual: Volume 1":
  https://github.com/riscv/riscv-isa-manual/releases

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for 'Zfa' extension.
	(riscv_multi_subset_supports_ext): Likewise.
	(riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency.

gas/ChangeLog:

	* config/tc-riscv.c (flt_lookup): New helper to lookup a float value
	in an array.
	(validate_riscv_insn): Add 'Wfv' as new format string directive.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Add floating-point chapter and describe
	limiations of the Zfa FP literal parsing.
	* testsuite/gas/riscv/zfa-32.d: New test.
	* testsuite/gas/riscv/zfa-32.s: New test.
	* testsuite/gas/riscv/zfa-64.d: New test.
	* testsuite/gas/riscv/zfa-64.s: New test.
	* testsuite/gas/riscv/zfa-fail.d: New test.
	* testsuite/gas/riscv/zfa-fail.l: New test.
	* testsuite/gas/riscv/zfa-fail.s: New test.
	* testsuite/gas/riscv/zfa.d: New test.
	* testsuite/gas/riscv/zfa.s: New test.
	* testsuite/gas/riscv/zfa.s: New test.

	* opcode/riscv-opc.h (MATCH_FLI_H): New.
	(MASK_FLI_H): New.
	(MATCH_FMINM_H): New.
	(MASK_FMINM_H): New.
	(MATCH_FMAXM_H): New.
	(MASK_FMAXM_H): New.
	(MATCH_FROUND_H): New.
	(MASK_FROUND_H): New.
	(MATCH_FROUNDNX_H): New.
	(MASK_FROUNDNX_H): New.
	(MATCH_FLTQ_H): New.
	(MASK_FLTQ_H): New.
	(MATCH_FLEQ_H): New.
	(MASK_FLEQ_H): New.
	(MATCH_FLI_S): New.
	(MASK_FLI_S): New.
	(MATCH_FMINM_S): New.
	(MASK_FMINM_S): New.
	(MATCH_FMAXM_S): New.
	(MASK_FMAXM_S): New.
	(MATCH_FROUND_S): New.
	(MASK_FROUND_S): New.
	(MATCH_FROUNDNX_S): New.
	(MASK_FROUNDNX_S): New.
	(MATCH_FLTQ_S): New.
	(MASK_FLTQ_S): New.
	(MATCH_FLEQ_S): New.
	(MASK_FLEQ_S): New.
	(MATCH_FLI_D): New.
	(MASK_FLI_D): New.
	(MATCH_FMINM_D): New.
	(MASK_FMINM_D): New.
	(MATCH_FMAXM_D): New.
	(MASK_FMAXM_D): New.
	(MATCH_FROUND_D): New.
	(MASK_FROUND_D): New.
	(MATCH_FROUNDNX_D): New.
	(MASK_FROUNDNX_D): New.
	(MATCH_FLTQ_D): New.
	(MASK_FLTQ_D): New.
	(MATCH_FLEQ_D): New.
	(MASK_FLEQ_D): New.
	(MATCH_FLI_Q): New.
	(MASK_FLI_Q): New.
	(MATCH_FMINM_Q): New.
	(MASK_FMINM_Q): New.
	(MATCH_FMAXM_Q): New.
	(MASK_FMAXM_Q): New.
	(MATCH_FROUND_Q): New.
	(MASK_FROUND_Q): New.
	(MATCH_FROUNDNX_Q): New.
	(MASK_FROUNDNX_Q): New.
	(MATCH_FLTQ_Q): New.
	(MASK_FLTQ_Q): New.
	(MATCH_FLEQ_Q): New.
	(MASK_FLEQ_Q): New.
	(MATCH_FCVTMOD_W_D): New.
	(MASK_FCVTMOD_W_D): New.
	(MATCH_FMVH_X_D): New.
	(MASK_FMVH_X_D): New.
	(MATCH_FMVH_X_Q): New.
	(MASK_FMVH_X_Q): New.
	(MATCH_FMVP_D_X): New.
	(MASK_FMVP_D_X): New.
	(MATCH_FMVP_Q_X): New.
	(MASK_FMVP_Q_X): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction
	classes for the Zfa extension.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add support for
	new format string directive 'Wfv'.
	* riscv-opc.c: Add Zfa instructions.

Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 108baeb..576cd24 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -595,6 +595,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    goto undefined_modifier;
 		  }
 		  break;
+	      case 'f':
+		switch (*++oparg)
+		  {
+		  case 'v':
+		    if (riscv_fli_symval[rs1])
+		      print (info->stream, dis_style_text, "%s",
+			     riscv_fli_symval[rs1]);
+		    else
+		      print (info->stream, dis_style_immediate, "%a",
+			     riscv_fli_numval[rs1]);
+		    break;
+		  default:
+		    goto undefined_modifier;
+		  }
+		break;
 	      default:
 		goto undefined_modifier;
 	      }
@@ -643,6 +658,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      }
 	  }
 	  break;
+
 	default:
 	undefined_modifier:
 	  /* xgettext:c-format */