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path: root/opcodes/aarch64-opc.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+23
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+12
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+22
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+21
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+12
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-17/+54
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-2/+57
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-4/+58
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-4/+44
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-4/+75
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+13
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-9/+48
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-8/+41
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-1/+1
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford1-1/+1
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-23/+51
2023-03-30aarch64: Sort fields alphanumericallyRichard Sandiford1-81/+81
2023-03-30aarch64: Resync field namesRichard Sandiford1-7/+7
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-8/+8
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-0/+13
2023-03-30aarch64: Try to report invalid variants against the closest matchRichard Sandiford1-17/+27
2023-03-30aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford1-1/+1
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-10/+9
2023-03-30aarch64: Commonise checks for index operandsRichard Sandiford1-18/+32
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-6/+14
2023-03-30aarch64: Move w12-w15 range check to libopcodesRichard Sandiford1-6/+20
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-0/+45
2023-03-30aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford1-3/+3
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-10/+10
2023-03-30aarch64: Restrict range of PRFM opcodesRichard Sandiford1-0/+9
2023-02-28[Aarch64] Add Binutils support for MECRichard Ball1-0/+9
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-0/+5
2022-10-17aarch64: Tweak handling of F_STRICTRichard Sandiford1-17/+8
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-145/+300
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-6/+16
2022-03-31aarch64: Relax check for RNG system registersRichard Sandiford1-1/+1
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford1-0/+2
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-5/+90
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+41
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford1-0/+5
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford1-0/+1
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-26/+22
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford1-35/+22
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford1-1/+166
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford1-4/+6
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