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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:09 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:09 +0100 |
| commit | 1d1060427db0fe4332d5ae34487789d57e873b5c (patch) | |
| tree | a95e9f2fa3a7d34fa20cf206fe563439377e334a /opcodes/aarch64-opc.c | |
| parent | 2f4e3a2c823f7a51630253cd8a8681203b86664b (diff) | |
| download | gdb-1d1060427db0fe4332d5ae34487789d57e873b5c.zip gdb-1d1060427db0fe4332d5ae34487789d57e873b5c.tar.gz gdb-1d1060427db0fe4332d5ae34487789d57e873b5c.tar.bz2 | |
aarch64: Regularise FLD_* suffixes
Some FLD_imm* suffixes used a counting scheme such as FLD_immN,
FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the
suffix. The latter seems more mnemonic, and was a big help
in doing the SME2 work.
Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious.
Presumably it indicated a 2-bit field, but it actually starts
in bit 22.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 7a88c19..46c49dd 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -239,11 +239,11 @@ const aarch64_field fields[] = { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */ { 22, 2 }, /* type: floating point type field in fp data inst. */ { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */ - { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */ - { 15, 6 }, /* imm6_2: in rmif instructions. */ - { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */ - { 0, 4 }, /* imm4_2: in rmif instructions. */ - { 10, 4 }, /* imm4_3: in adddg/subg instructions. */ + { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */ + { 15, 6 }, /* imm6_15: in rmif instructions. */ + { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */ + { 0, 4 }, /* imm4_0: in rmif instructions. */ + { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */ @@ -251,8 +251,8 @@ const aarch64_field fields[] = { 12, 9 }, /* imm9: in load/store pre/post index instructions. */ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ { 5, 14 }, /* imm14: in test bit and branch instructions. */ - { 5, 16 }, /* imm16: in exception instructions. */ - { 0, 16 }, /* imm16_2: in udf instruction. */ + { 5, 16 }, /* imm16_5: in exception instructions. */ + { 0, 16 }, /* imm16_0: in udf instruction. */ { 0, 26 }, /* imm26: in unconditional branch instructions. */ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */ @@ -326,7 +326,7 @@ const aarch64_field fields[] = { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ - { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */ + { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ |