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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
| commit | abd542a2f1e15303ea4a9bf05d1a937b5162df5e (patch) | |
| tree | 34a1279f78aba258499fe9084f32931339e6452e /opcodes/aarch64-opc.c | |
| parent | 60336e19658f1b820753ac09797f14b26e594cfa (diff) | |
| download | gdb-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.zip gdb-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.tar.gz gdb-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.tar.bz2 | |
aarch64: Add a _10 suffix to FLD_imm3
SME2 adds various new 3-bit immediate fields, so this patch adds
an lsb position suffix to the name of the field that we already have.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1a1e1bd..969362a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -296,7 +296,7 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ - { 10, 3 }, /* imm3: in add/sub extended reg instructions. */ + { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ |