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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
| commit | ce623e7aa486d1330c9a4529c77a302d2fdcb801 (patch) | |
| tree | 0eb2f066a02a0cd040e95eeb05c40a4aea975cec /opcodes/aarch64-opc.c | |
| parent | c04965ec7d8819448f7d7b48cee9fa6567e67455 (diff) | |
| download | gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.zip gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.tar.gz gdb-ce623e7aa486d1330c9a4529c77a302d2fdcb801.tar.bz2 | |
aarch64: Add the SME2 saturating conversion instructions
There are two instruction formats here:
- SQCVT, SQCVTU and UQCVT, which operate on lists of two or
four registers.
- SQCVTN, SQCVTUN and UQCVTN, which operate on lists of
four registers.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ac54bf7..0418a21 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -252,6 +252,7 @@ const aarch64_field fields[] = { 23, 1 }, /* SME_i1: immediate field, bit 23. */ { 12, 2 }, /* SME_size_12: bits [13:12]. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ + { 23, 1 }, /* SME_sz_23: bit [23]. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ |