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2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma1-0/+12
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma1-0/+12
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma2-1/+37
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma1-0/+169
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma1-0/+33
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-0/+7
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+1
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-1/+20
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-1/+4
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-1/+13
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-1/+10
2023-11-10bfd, binutils: add gfx11 amdgpu architecturesSimon Marchi2-0/+9
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang1-38/+81
2023-11-10Add ability to change linker warning messages into errors when reporting exec...Nick Clifton2-8/+37
2023-11-10Add support for ilp32 register alias.Lulu Cai1-4/+4
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+3
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+2
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento1-0/+2
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2-0/+72
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2-0/+44
2023-11-06RISC-V: Moved out linker internal relocations after R_RISCV_max.Nelson Chu1-0/+8
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+3
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni1-0/+2
2023-11-02aarch64: Add support for GCS extension.srinath1-1/+3
2023-11-02aarch64: Add support for Check Feature Status Extension.Srinath Parvathaneni1-2/+5
2023-11-02aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.srinath1-1/+8
2023-10-30Accept and ignore the R_BPF_64_NODLYD32 relocation.Nick Clifton2-2/+7
2023-10-20bfd: microblaze: Add 32_NONE reloc typeNeal Frager1-0/+1
2023-10-19RISC-V: Remove semicolons from DECLARE_INSNTsukasa OI1-15/+15
2023-10-17RISC-V: Fix typoTsukasa OI1-1/+1
2023-10-10LoongArch/GAS: Add support for branch relaxationmengqinggang1-0/+12
2023-10-08as: add option for generate R_LARCH_32/64_PCREL.cailulu1-0/+1
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-1/+0
2023-10-06gdb: support rseq auxvsIlya Leoshkevich1-0/+2
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-0/+1
2023-10-04aarch64: system register aliasing detectionVictor Do Nascimento1-0/+1
2023-09-29x86-64: Add -z mark-plt and -z nomark-pltH.J. Lu1-0/+5
2023-09-28Add support to readelf for the PT_OPENBSD_NOBTCFI segment type.Frederic Cambus2-0/+5
2023-09-26aarch64: Allow feature flags to occupy >64 bitsRichard Sandiford1-23/+39
2023-09-26aarch64: Restructure feature flag handlingRichard Sandiford1-151/+268
2023-09-25Revert "arc: Update opcode related include files for ARCv3."Claudiu Zissulescu6-452/+96
2023-09-25arc: Update opcode related include files for ARCv3.Claudiu Zissulescu6-96/+452
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-1/+0
2023-09-05RISC-V: Add 'Smcntrpmf' extension and its CSRsTsukasa OI1-4/+12
2023-08-27PE dos_messageAlan Modra3-3/+3
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento1-54/+54
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-2/+2
2023-08-21aarch64/sme2: Teach binutils/BFD about the NT_ARM_ZT register setLuis Machado1-0/+2
2023-08-16kvx: New port.Paul Iannetta4-0/+3356
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-0/+1
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