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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-10-30 11:47:23 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-07 21:53:59 +0000 |
| commit | 6219f9dae7d04b52ef171e0aa3341bf977b05a68 (patch) | |
| tree | d228c4c76f5941fbcfa736fcc3584f0d7d523893 /include | |
| parent | ecd4c78dddefe41d9fc7b947fdf4e76b743b2b02 (diff) | |
| download | gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.zip gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.tar.gz gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.tar.bz2 | |
aarch64: Add LSE128 instruction operand support
Given the particular encoding of the LSE128 instructions, create the
necessary shared input+output operand register description and
handling in the code to allow for the encoding of the LSE128 128-bit
atomic operations.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands):
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd):
opcodes/ChangeLog:
* aarch64-opc.c (fields):
(aarch64_print_operand):
* aarch64-opc.h (enum aarch64_field_kind):
* aarch64-tbl.h (AARCH64_OPERANDS):
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index c081760..1ede570 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -521,6 +521,8 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ + AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */ + AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ |