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path: root/include/opcode/riscv.h
AgeCommit message (Expand)AuthorFilesLines
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+4
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-2/+4
2020-12-01RISC-V: Support to add implicit extensions for G.Nelson Chu1-0/+2
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu1-2/+2
2020-08-31PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra1-4/+4
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-0/+1
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-4/+0
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu1-1/+0
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-3/+2
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-0/+76
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-3/+20
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+6
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-1/+1
2018-11-27RISC-V: Add .insn CA support.Jim Wilson1-0/+4
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-2/+8
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+21
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman1-1/+1
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+2
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+342