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| author | Jim Wilson <jimw@sifive.com> | 2018-03-14 16:04:03 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-03-14 16:04:03 -0700 |
| commit | 0e35537d754f1c687850d1caccb2d78d2e418391 (patch) | |
| tree | 61e8574058def02b9f33ceba1eab999e575cad8e /include/opcode/riscv.h | |
| parent | 3ae9ce5dd7d1119ca2c94c63a07b04921048ebe3 (diff) | |
| download | gdb-0e35537d754f1c687850d1caccb2d78d2e418391.zip gdb-0e35537d754f1c687850d1caccb2d78d2e418391.tar.gz gdb-0e35537d754f1c687850d1caccb2d78d2e418391.tar.bz2 | |
RISC-V: Add .insn support.
gas/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (opcode_name_list): New.
(opcode_names_hash): Likewise.
(init_opcode_names_hash): Likewise.
(opcode_name_lookup): Likewise.
(validate_riscv_insn): New argument length, and add new format
which used in .insn directive.
(md_begin): Refine hash table initialization logic into
init_opcode_hash.
(init_opcode_hash): New.
(my_getOpcodeExpression): Parse opcode name for .insn.
(riscv_ip): New argument hash, able to handle .insn directive.
(s_riscv_insn): Handler for .insn directive.
(riscv_pseudo_table): New entry for .insn.
* doc/c-riscv.texi: Add documentation for .insn directive.
* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
* testsuite/gas/riscv/insn.s: Likewise.
include/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* opcode/riscv.h (OP_MASK_FUNCT3): New.
(OP_SH_FUNCT3): Likewise.
(OP_MASK_FUNCT7): Likewise.
(OP_SH_FUNCT7): Likewise.
(OP_MASK_OP2): Likewise.
(OP_SH_OP2): Likewise.
(OP_MASK_CFUNCT4): Likewise.
(OP_SH_CFUNCT4): Likewise.
(OP_MASK_CFUNCT3): Likewise.
(OP_SH_CFUNCT3): Likewise.
(riscv_insn_types): Likewise.
opcodes/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_insn_types): New.
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b87c719..ac6f773 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -77,6 +77,8 @@ static const char * const riscv_pred_succ[16] = (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) #define EXTRACT_RVC_SIMM3(x) \ (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) +#define EXTRACT_RVC_UIMM8(x) \ + (RV_X(x, 5, 8)) #define EXTRACT_RVC_ADDI4SPN_IMM(x) \ ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) #define EXTRACT_RVC_ADDI16SP_IMM(x) \ @@ -114,6 +116,8 @@ static const char * const riscv_pred_succ[16] = ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) #define ENCODE_RVC_SIMM3(x) \ (RV_X(x, 0, 3) << 10) +#define ENCODE_RVC_UIMM8(x) \ + (RV_X(x, 0, 8) << 5) #define ENCODE_RVC_ADDI4SPN_IMM(x) \ ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) #define ENCODE_RVC_ADDI16SP_IMM(x) \ @@ -143,6 +147,7 @@ static const char * const riscv_pred_succ[16] = #define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) #define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) #define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) +#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x)) #define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) #define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) #define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x)) @@ -223,8 +228,18 @@ static const char * const riscv_pred_succ[16] = #define OP_MASK_CSR 0xfff #define OP_SH_CSR 20 +#define OP_MASK_FUNCT3 0x7 +#define OP_SH_FUNCT3 12 +#define OP_MASK_FUNCT7 0x7f +#define OP_SH_FUNCT7 25 +#define OP_MASK_FUNCT2 0x3 +#define OP_SH_FUNCT2 25 + /* RVC fields. */ +#define OP_MASK_OP2 0x3 +#define OP_SH_OP2 0 + #define OP_MASK_CRS2 0x1f #define OP_SH_CRS2 2 #define OP_MASK_CRS1S 0x7 @@ -232,6 +247,11 @@ static const char * const riscv_pred_succ[16] = #define OP_MASK_CRS2S 0x7 #define OP_SH_CRS2S 2 +#define OP_MASK_CFUNCT4 0xf +#define OP_SH_CFUNCT4 12 +#define OP_MASK_CFUNCT3 0x7 +#define OP_SH_CFUNCT3 13 + /* ABI names for selected x-registers. */ #define X_RA 1 @@ -340,5 +360,6 @@ extern const char * const riscv_fpr_names_numeric[NFPR]; extern const char * const riscv_fpr_names_abi[NFPR]; extern const struct riscv_opcode riscv_opcodes[]; +extern const struct riscv_opcode riscv_insn_types[]; #endif /* _RISCV_H_ */ |