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| author | Kito Cheng <kito.cheng@gmail.com> | 2017-01-03 17:42:01 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-01-03 17:42:01 +0000 |
| commit | cc917fd93d2a836adfd61b91df021cf835e88fd1 (patch) | |
| tree | 27bd4adc36ad4418cd312b6b3552df1f650287e1 /include/opcode/riscv.h | |
| parent | de1010f40884537cf0905ad134162cd2db71dc2a (diff) | |
| download | gdb-cc917fd93d2a836adfd61b91df021cf835e88fd1.zip gdb-cc917fd93d2a836adfd61b91df021cf835e88fd1.tar.gz gdb-cc917fd93d2a836adfd61b91df021cf835e88fd1.tar.bz2 | |
Add support for the Q extension to the RISCV ISA.
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b21e8c9..719565d 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -323,8 +323,10 @@ enum M_SD, M_FLW, M_FLD, + M_FLQ, M_FSW, M_FSD, + M_FSQ, M_CALL, M_J, M_LI, |