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2019-09-23ecoff bfd.h tidyAlan Modra3-0/+7
2019-09-23arm bfd.h tidyAlan Modra2-0/+5
2019-09-21tc-i386.c gcc10 warning fixAlan Modra2-2/+6
2019-09-20bfd macro conversion to inline functions, sectionAlan Modra2-1/+5
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich4-4/+25
2019-09-19[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson2-0/+10
2019-09-19bfd_section_* macrosAlan Modra73-370/+358
2019-09-18bfd_asymbol_* macrosAlan Modra2-2/+7
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi4-22/+14
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2-7/+26
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell4-18/+36
2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc a...Nick Clifton3-0/+41
2019-09-10[PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni6-0/+177
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell2-0/+6
2019-09-05PowerPC warning on symbol+offset@gotAlan Modra2-3/+8
2019-08-30[PATCH][ARM][GAS]: Assembler support to interpret MVE VMOV instruction correc...Srinath Parvathaneni3-1/+86
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni5-202/+243
2019-08-25RISC-V: Improve li expansion for better code density.Kito Cheng5-5/+108
2019-08-23Updated Swedish translation for the gas sub-directory.Nick Clifton2-49/+26
2019-08-22Arm: Add support for missing CPUsDennis Zhang6-0/+39
2019-08-22Fix the assembler's floating point number parser so that it can correctly han...Bosco Garc?a5-7/+49
2019-08-22Implement a float16 directive for assembling 16 bit IEEE 754 floating point n...Barnaby Wilks7-5/+70
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov2-10/+15
2019-08-20Remove test files for a different patch accidentally committed with patch for...Nick Clifton2-35/+0
2019-08-20Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77...Dennis Zhang12-0/+112
2019-08-19MIPS/gas: Fix misaligned address errors to disregard ISA mode bitFaraz Shahbazker2-5/+32
2019-08-19MIPS/gas: Retain ISA mode bit for labels with .insn annotationFaraz Shahbazker5-3/+45
2019-08-19Float16: Fix test failures for non ELF targetsBarnaby Wilks2-27/+26
2019-08-15Updatesd Swdish translation for the gas sub-directory.Nick Clifton2-872/+466
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni6-8/+76
2019-08-12Add generic and ARM specific support for half-precision IEEE 754 floating poi...Barnaby Wilks20-8/+324
2019-08-12PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1Alan Modra2-17/+28
2019-08-09x86-64: generalize SIMD test expectationsJan Beulich7-927/+212
2019-08-08Change the output of readelf's note display so that the "Data size" column he...Nick Clifton5-4/+13
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ...Yoshinori Sato1-4/+4
2019-08-08Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.Yoshinori Sato5-50/+56
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks12-2712/+55
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson5-1/+71
2019-07-24Update the Swedish translation for the gas sub-directory.Nick Clifton2-4191/+5083
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu2-1/+5
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra4-2/+11
2019-07-24Define ELF_OSABI for visiumAlan Modra4-5/+16
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov4-0/+9
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra6-29/+65
2019-07-23gas "mbind sections" testAlan Modra2-2/+4
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks10-137/+136
2019-07-19x86: Pass -O0 to assembler in noextreg.dH.J. Lu2-0/+5
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi7-52/+60
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi2-1/+49
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford8-7/+17