aboutsummaryrefslogtreecommitdiff
path: root/gas
diff options
context:
space:
mode:
authorJan Beulich <jbeulich@suse.com>2019-09-20 10:18:15 +0200
committerJan Beulich <jbeulich@suse.com>2019-09-20 10:18:15 +0200
commit3f9aad111cea2f25877d0a6b404956769c14faee (patch)
tree710516f16c6e7652447adce60a180cdd6f9e2362 /gas
parent4c51dacacf8a97194a1241ad5e1cbf7be00a59a3 (diff)
downloadgdb-3f9aad111cea2f25877d0a6b404956769c14faee.zip
gdb-3f9aad111cea2f25877d0a6b404956769c14faee.tar.gz
gdb-3f9aad111cea2f25877d0a6b404956769c14faee.tar.bz2
x86-64: fix handling of PUSH/POP of segment register
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog9
-rw-r--r--gas/config/tc-i386.c4
-rw-r--r--gas/testsuite/gas/i386/x86-64-opcode.d6
-rw-r--r--gas/testsuite/gas/i386/x86-64-opcode.s10
4 files changed, 25 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b4234f0..bcd2f9a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2018-09-20 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/25012
+ * config/tc-i386.c (process_operands): Adjust handling of
+ PUSH/POP of segment registers.
+ * testsuite/gas/i386/x86-64-opcode.s: Add PUSHq/POPq case with
+ %fs/%gs operands. Add PUSHF/POPF case without suffix.
+ * testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
+
2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* NEWS: Add SVE2 and TME entries.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fec69c1..349b36d 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7010,14 +7010,14 @@ duplicate:
if (flag_code != CODE_64BIT
? i.tm.base_opcode == POP_SEG_SHORT
&& i.op[0].regs->reg_num == 1
- : (i.tm.base_opcode | 1) == POP_SEG_SHORT
+ : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
&& i.op[0].regs->reg_num < 4)
{
as_bad (_("you can't `%s %s%s'"),
i.tm.name, register_prefix, i.op[0].regs->reg_name);
return 0;
}
- if ( i.op[0].regs->reg_num > 3 )
+ if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
{
i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
i.tm.opcode_length = 2;
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index 35829f4..d8a1e44 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -255,13 +255,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\)
[ ]*[a-f0-9]+: 8f 00 popq \(%rax\)
[ ]*[a-f0-9]+: 0f a1 popq %fs
+[ ]*[a-f0-9]+: 0f a1 popq %fs
+[ ]*[a-f0-9]+: 0f a9 popq %gs
[ ]*[a-f0-9]+: 0f a9 popq %gs
[ ]*[a-f0-9]+: 9d popfq
+[ ]*[a-f0-9]+: 9d popfq
[ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\)
[ ]*[a-f0-9]+: ff 30 pushq \(%rax\)
[ ]*[a-f0-9]+: 0f a0 pushq %fs
+[ ]*[a-f0-9]+: 0f a0 pushq %fs
+[ ]*[a-f0-9]+: 0f a8 pushq %gs
[ ]*[a-f0-9]+: 0f a8 pushq %gs
[ ]*[a-f0-9]+: 9c pushfq
+[ ]*[a-f0-9]+: 9c pushfq
[ ]*[a-f0-9]+: 0f 77 emms
[ ]*[a-f0-9]+: 0f 0e femms
[ ]*[a-f0-9]+: 0f 08 invd
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index 8d4a6ed..caee124 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -323,15 +323,21 @@
POPq (%r8) # -- -- -- 41 8F 00 ; REX to access upper reg.
POPq (%rax) # -- -- -- -- 8F 00
POP %fs # -- -- -- -- 0F A1
+ POPq %fs # -- -- -- -- 0F A1
POP %gs # -- -- -- -- 0F A9
- POPFQ # -- -- -- -- 9D
+ POPq %gs # -- -- -- -- 0F A9
+ POPF # -- -- -- -- 9D
+ POPFq # -- -- -- -- 9D
# PUSH
PUSHq (%r8) # -- -- -- 41 FF 30 ; REX to access upper reg.
PUSHq (%rax) # -- -- -- -- FF 30
PUSH %fs # -- -- -- -- 0F A0
+ PUSHq %fs # -- -- -- -- 0F A0
PUSH %gs # -- -- -- -- 0F A8
- PUSHFQ # -- -- -- -- 9C
+ PUSHq %gs # -- -- -- -- 0F A8
+ PUSHF # -- -- -- -- 9C
+ PUSHFq # -- -- -- -- 9C